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authorYonghong Song <ysong@broadcom.com>2013-12-21 15:22:16 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-01-25 01:39:47 +0400
commited8dfc46e0099540cb923f61bca885b460f1365e (patch)
treed7856bf6134c31844729669663a8d8917e74c4ae /mm/pagewalk.c
parentd3b94285025732379df8a46c02416400c70daa85 (diff)
downloadlinux-ed8dfc46e0099540cb923f61bca885b460f1365e.tar.xz
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6276/
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