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| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-06-05 18:05:51 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-06-07 00:21:06 +0300 |
| commit | 40ae25505fe834648ce4aa70b073ee934942bfdb (patch) | |
| tree | eb05d79c9776b8b6e742eab7cdc958fbc60c0018 /lib/locking-selftest-spin-softirq.h | |
| parent | b637e0856a6248230e53b5465ab0751f27fdf320 (diff) | |
| download | linux-40ae25505fe834648ce4aa70b073ee934942bfdb.tar.xz | |
net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'lib/locking-selftest-spin-softirq.h')
0 files changed, 0 insertions, 0 deletions