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authorJon Hunter <jonathanh@nvidia.com>2015-05-05 17:17:52 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-05-10 20:12:18 +0300
commit245c0278ab2a2e3d0360296710b4c285291469b5 (patch)
tree30fb45f2883375fc903d9f0500e5fff0c2c8d292 /lib/locking-selftest-rlock-softirq.h
parent7a7a7e6d9b8f78e73b45bdc436c5fbdbb7220c74 (diff)
downloadlinux-245c0278ab2a2e3d0360296710b4c285291469b5.tar.xz
serial: tegra: Correct delay after TX flush
For all tegra devices (up to t210), there is a hardware issue that requires software to wait for 32 UART clock periods for the flush to propagate otherwise TX data could be post. Add a helper function to wait for N UART clock periods and update delay following FIFO flush to be 32 UART clock cycles. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'lib/locking-selftest-rlock-softirq.h')
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