diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-07-29 12:17:53 +0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-11-26 11:43:23 +0300 |
| commit | 4f4f85fa0b96a35429ebb4bc278d70ae0f72113c (patch) | |
| tree | 566618d20763f01c8a8b66fa1fe5f621373c4123 /include | |
| parent | 7f06dd61248a75668bbb39b6fcca6ff407745df8 (diff) | |
| download | linux-4f4f85fa0b96a35429ebb4bc278d70ae0f72113c.tar.xz | |
clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.
Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/tegra114-car.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/tegra124-car.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/tegra20-car.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index fc12621fb432..534c03f8ad72 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -49,7 +49,7 @@ #define TEGRA114_CLK_I2S0 30 /* 31 */ -/* 32 */ +#define TEGRA114_CLK_MC 32 /* 33 */ #define TEGRA114_CLK_APBDMA 34 /* 35 */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h index 6bac637fd635..af9bc9a3ddbc 100644 --- a/include/dt-bindings/clock/tegra124-car.h +++ b/include/dt-bindings/clock/tegra124-car.h @@ -48,7 +48,7 @@ #define TEGRA124_CLK_I2S0 30 /* 31 */ -/* 32 */ +#define TEGRA124_CLK_MC 32 /* 33 */ #define TEGRA124_CLK_APBDMA 34 /* 35 */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h index 9406207cfac8..04500b243a4d 100644 --- a/include/dt-bindings/clock/tegra20-car.h +++ b/include/dt-bindings/clock/tegra20-car.h @@ -49,7 +49,7 @@ /* 30 */ #define TEGRA20_CLK_CACHE2 31 -#define TEGRA20_CLK_MEM 32 +#define TEGRA20_CLK_MC 32 #define TEGRA20_CLK_AHBDMA 33 #define TEGRA20_CLK_APBDMA 34 /* 35 */ |