diff options
author | Olof Johansson <olof@lixom.net> | 2019-01-05 01:30:36 +0300 |
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committer | Olof Johansson <olof@lixom.net> | 2019-01-05 01:31:38 +0300 |
commit | 00f8ccd0c95f4e604297057a5bccec86c0903d14 (patch) | |
tree | 3ef930b38f7341be627da106f6ec31a007c207e4 /include | |
parent | 8e564895c30ca73cd9788aecb845879ddee987c3 (diff) | |
parent | 3e730e858139c3bed9587ca50ce0f2aa12fe9523 (diff) | |
download | linux-00f8ccd0c95f4e604297057a5bccec86c0903d14.tar.xz |
Merge branch 'next/drivers' into next/late
Merge in a few missing patches from the pull request (my copy of the
branch was behind the staged version in linux-next).
* next/drivers:
memory: pl353: Add driver for arm pl353 static memory controller
dt-bindings: memory: Add pl353 smc controller devicetree binding information
firmware: qcom: scm: fix compilation error when disabled
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/firmware/imx/rsrc.h | 559 | ||||
-rw-r--r-- | include/dt-bindings/power/imx8mq-power.h | 21 | ||||
-rw-r--r-- | include/dt-bindings/power/r8a77970-sysc.h | 7 | ||||
-rw-r--r-- | include/dt-bindings/power/r8a77980-sysc.h | 6 | ||||
-rw-r--r-- | include/dt-bindings/power/raspberrypi-power.h | 5 | ||||
-rw-r--r-- | include/dt-bindings/power/rk3066-power.h | 22 | ||||
-rw-r--r-- | include/dt-bindings/power/rk3188-power.h | 24 | ||||
-rw-r--r-- | include/linux/dma/pxa-dma.h | 11 | ||||
-rw-r--r-- | include/linux/firmware/imx/sci.h | 1 | ||||
-rw-r--r-- | include/linux/firmware/imx/svc/pm.h | 85 | ||||
-rw-r--r-- | include/linux/firmware/imx/types.h | 552 | ||||
-rw-r--r-- | include/linux/pl353-smc.h | 30 | ||||
-rw-r--r-- | include/linux/qcom_scm.h | 3 | ||||
-rw-r--r-- | include/linux/soc/mediatek/mtk-cmdq.h | 133 | ||||
-rw-r--r-- | include/linux/soc/qcom/qmi.h | 2 | ||||
-rw-r--r-- | include/soc/bcm2835/raspberrypi-firmware.h | 5 | ||||
-rw-r--r-- | include/soc/qcom/cmd-db.h | 12 | ||||
-rw-r--r-- | include/soc/tegra/bpmp-abi.h | 1188 | ||||
-rw-r--r-- | include/soc/tegra/bpmp.h | 7 | ||||
-rw-r--r-- | include/soc/tegra/fuse.h | 1 | ||||
-rw-r--r-- | include/soc/tegra/pmc.h | 21 |
21 files changed, 1865 insertions, 830 deletions
diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h new file mode 100644 index 000000000000..4481f2d60d65 --- /dev/null +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -0,0 +1,559 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_RSCRC_IMX_H +#define __DT_BINDINGS_RSCRC_IMX_H + +/* + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ + +#define IMX_SC_R_A53 0 +#define IMX_SC_R_A53_0 1 +#define IMX_SC_R_A53_1 2 +#define IMX_SC_R_A53_2 3 +#define IMX_SC_R_A53_3 4 +#define IMX_SC_R_A72 5 +#define IMX_SC_R_A72_0 6 +#define IMX_SC_R_A72_1 7 +#define IMX_SC_R_A72_2 8 +#define IMX_SC_R_A72_3 9 +#define IMX_SC_R_CCI 10 +#define IMX_SC_R_DB 11 +#define IMX_SC_R_DRC_0 12 +#define IMX_SC_R_DRC_1 13 +#define IMX_SC_R_GIC_SMMU 14 +#define IMX_SC_R_IRQSTR_M4_0 15 +#define IMX_SC_R_IRQSTR_M4_1 16 +#define IMX_SC_R_SMMU 17 +#define IMX_SC_R_GIC 18 +#define IMX_SC_R_DC_0_BLIT0 19 +#define IMX_SC_R_DC_0_BLIT1 20 +#define IMX_SC_R_DC_0_BLIT2 21 +#define IMX_SC_R_DC_0_BLIT_OUT 22 +#define IMX_SC_R_DC_0_CAPTURE0 23 +#define IMX_SC_R_DC_0_CAPTURE1 24 +#define IMX_SC_R_DC_0_WARP 25 +#define IMX_SC_R_DC_0_INTEGRAL0 26 +#define IMX_SC_R_DC_0_INTEGRAL1 27 +#define IMX_SC_R_DC_0_VIDEO0 28 +#define IMX_SC_R_DC_0_VIDEO1 29 +#define IMX_SC_R_DC_0_FRAC0 30 +#define IMX_SC_R_DC_0_FRAC1 31 +#define IMX_SC_R_DC_0 32 +#define IMX_SC_R_GPU_2_PID0 33 +#define IMX_SC_R_DC_0_PLL_0 34 +#define IMX_SC_R_DC_0_PLL_1 35 +#define IMX_SC_R_DC_1_BLIT0 36 +#define IMX_SC_R_DC_1_BLIT1 37 +#define IMX_SC_R_DC_1_BLIT2 38 +#define IMX_SC_R_DC_1_BLIT_OUT 39 +#define IMX_SC_R_DC_1_CAPTURE0 40 +#define IMX_SC_R_DC_1_CAPTURE1 41 +#define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_DC_1_INTEGRAL0 43 +#define IMX_SC_R_DC_1_INTEGRAL1 44 +#define IMX_SC_R_DC_1_VIDEO0 45 +#define IMX_SC_R_DC_1_VIDEO1 46 +#define IMX_SC_R_DC_1_FRAC0 47 +#define IMX_SC_R_DC_1_FRAC1 48 +#define IMX_SC_R_DC_1 49 +#define IMX_SC_R_GPU_3_PID0 50 +#define IMX_SC_R_DC_1_PLL_0 51 +#define IMX_SC_R_DC_1_PLL_1 52 +#define IMX_SC_R_SPI_0 53 +#define IMX_SC_R_SPI_1 54 +#define IMX_SC_R_SPI_2 55 +#define IMX_SC_R_SPI_3 56 +#define IMX_SC_R_UART_0 57 +#define IMX_SC_R_UART_1 58 +#define IMX_SC_R_UART_2 59 +#define IMX_SC_R_UART_3 60 +#define IMX_SC_R_UART_4 61 +#define IMX_SC_R_EMVSIM_0 62 +#define IMX_SC_R_EMVSIM_1 63 +#define IMX_SC_R_DMA_0_CH0 64 +#define IMX_SC_R_DMA_0_CH1 65 +#define IMX_SC_R_DMA_0_CH2 66 +#define IMX_SC_R_DMA_0_CH3 67 +#define IMX_SC_R_DMA_0_CH4 68 +#define IMX_SC_R_DMA_0_CH5 69 +#define IMX_SC_R_DMA_0_CH6 70 +#define IMX_SC_R_DMA_0_CH7 71 +#define IMX_SC_R_DMA_0_CH8 72 +#define IMX_SC_R_DMA_0_CH9 73 +#define IMX_SC_R_DMA_0_CH10 74 +#define IMX_SC_R_DMA_0_CH11 75 +#define IMX_SC_R_DMA_0_CH12 76 +#define IMX_SC_R_DMA_0_CH13 77 +#define IMX_SC_R_DMA_0_CH14 78 +#define IMX_SC_R_DMA_0_CH15 79 +#define IMX_SC_R_DMA_0_CH16 80 +#define IMX_SC_R_DMA_0_CH17 81 +#define IMX_SC_R_DMA_0_CH18 82 +#define IMX_SC_R_DMA_0_CH19 83 +#define IMX_SC_R_DMA_0_CH20 84 +#define IMX_SC_R_DMA_0_CH21 85 +#define IMX_SC_R_DMA_0_CH22 86 +#define IMX_SC_R_DMA_0_CH23 87 +#define IMX_SC_R_DMA_0_CH24 88 +#define IMX_SC_R_DMA_0_CH25 89 +#define IMX_SC_R_DMA_0_CH26 90 +#define IMX_SC_R_DMA_0_CH27 91 +#define IMX_SC_R_DMA_0_CH28 92 +#define IMX_SC_R_DMA_0_CH29 93 +#define IMX_SC_R_DMA_0_CH30 94 +#define IMX_SC_R_DMA_0_CH31 95 +#define IMX_SC_R_I2C_0 96 +#define IMX_SC_R_I2C_1 97 +#define IMX_SC_R_I2C_2 98 +#define IMX_SC_R_I2C_3 99 +#define IMX_SC_R_I2C_4 100 +#define IMX_SC_R_ADC_0 101 +#define IMX_SC_R_ADC_1 102 +#define IMX_SC_R_FTM_0 103 +#define IMX_SC_R_FTM_1 104 +#define IMX_SC_R_CAN_0 105 +#define IMX_SC_R_CAN_1 106 +#define IMX_SC_R_CAN_2 107 +#define IMX_SC_R_DMA_1_CH0 108 +#define IMX_SC_R_DMA_1_CH1 109 +#define IMX_SC_R_DMA_1_CH2 110 +#define IMX_SC_R_DMA_1_CH3 111 +#define IMX_SC_R_DMA_1_CH4 112 +#define IMX_SC_R_DMA_1_CH5 113 +#define IMX_SC_R_DMA_1_CH6 114 +#define IMX_SC_R_DMA_1_CH7 115 +#define IMX_SC_R_DMA_1_CH8 116 +#define IMX_SC_R_DMA_1_CH9 117 +#define IMX_SC_R_DMA_1_CH10 118 +#define IMX_SC_R_DMA_1_CH11 119 +#define IMX_SC_R_DMA_1_CH12 120 +#define IMX_SC_R_DMA_1_CH13 121 +#define IMX_SC_R_DMA_1_CH14 122 +#define IMX_SC_R_DMA_1_CH15 123 +#define IMX_SC_R_DMA_1_CH16 124 +#define IMX_SC_R_DMA_1_CH17 125 +#define IMX_SC_R_DMA_1_CH18 126 +#define IMX_SC_R_DMA_1_CH19 127 +#define IMX_SC_R_DMA_1_CH20 128 +#define IMX_SC_R_DMA_1_CH21 129 +#define IMX_SC_R_DMA_1_CH22 130 +#define IMX_SC_R_DMA_1_CH23 131 +#define IMX_SC_R_DMA_1_CH24 132 +#define IMX_SC_R_DMA_1_CH25 133 +#define IMX_SC_R_DMA_1_CH26 134 +#define IMX_SC_R_DMA_1_CH27 135 +#define IMX_SC_R_DMA_1_CH28 136 +#define IMX_SC_R_DMA_1_CH29 137 +#define IMX_SC_R_DMA_1_CH30 138 +#define IMX_SC_R_DMA_1_CH31 139 +#define IMX_SC_R_UNUSED1 140 +#define IMX_SC_R_UNUSED2 141 +#define IMX_SC_R_UNUSED3 142 +#define IMX_SC_R_UNUSED4 143 +#define IMX_SC_R_GPU_0_PID0 144 +#define IMX_SC_R_GPU_0_PID1 145 +#define IMX_SC_R_GPU_0_PID2 146 +#define IMX_SC_R_GPU_0_PID3 147 +#define IMX_SC_R_GPU_1_PID0 148 +#define IMX_SC_R_GPU_1_PID1 149 +#define IMX_SC_R_GPU_1_PID2 150 +#define IMX_SC_R_GPU_1_PID3 151 +#define IMX_SC_R_PCIE_A 152 +#define IMX_SC_R_SERDES_0 153 +#define IMX_SC_R_MATCH_0 154 +#define IMX_SC_R_MATCH_1 155 +#define IMX_SC_R_MATCH_2 156 +#define IMX_SC_R_MATCH_3 157 +#define IMX_SC_R_MATCH_4 158 +#define IMX_SC_R_MATCH_5 159 +#define IMX_SC_R_MATCH_6 160 +#define IMX_SC_R_MATCH_7 161 +#define IMX_SC_R_MATCH_8 162 +#define IMX_SC_R_MATCH_9 163 +#define IMX_SC_R_MATCH_10 164 +#define IMX_SC_R_MATCH_11 165 +#define IMX_SC_R_MATCH_12 166 +#define IMX_SC_R_MATCH_13 167 +#define IMX_SC_R_MATCH_14 168 +#define IMX_SC_R_PCIE_B 169 +#define IMX_SC_R_SATA_0 170 +#define IMX_SC_R_SERDES_1 171 +#define IMX_SC_R_HSIO_GPIO 172 +#define IMX_SC_R_MATCH_15 173 +#define IMX_SC_R_MATCH_16 174 +#define IMX_SC_R_MATCH_17 175 +#define IMX_SC_R_MATCH_18 176 +#define IMX_SC_R_MATCH_19 177 +#define IMX_SC_R_MATCH_20 178 +#define IMX_SC_R_MATCH_21 179 +#define IMX_SC_R_MATCH_22 180 +#define IMX_SC_R_MATCH_23 181 +#define IMX_SC_R_MATCH_24 182 +#define IMX_SC_R_MATCH_25 183 +#define IMX_SC_R_MATCH_26 184 +#define IMX_SC_R_MATCH_27 185 +#define IMX_SC_R_MATCH_28 186 +#define IMX_SC_R_LCD_0 187 +#define IMX_SC_R_LCD_0_PWM_0 188 +#define IMX_SC_R_LCD_0_I2C_0 189 +#define IMX_SC_R_LCD_0_I2C_1 190 +#define IMX_SC_R_PWM_0 191 +#define IMX_SC_R_PWM_1 192 +#define IMX_SC_R_PWM_2 193 +#define IMX_SC_R_PWM_3 194 +#define IMX_SC_R_PWM_4 195 +#define IMX_SC_R_PWM_5 196 +#define IMX_SC_R_PWM_6 197 +#define IMX_SC_R_PWM_7 198 +#define IMX_SC_R_GPIO_0 199 +#define IMX_SC_R_GPIO_1 200 +#define IMX_SC_R_GPIO_2 201 +#define IMX_SC_R_GPIO_3 202 +#define IMX_SC_R_GPIO_4 203 +#define IMX_SC_R_GPIO_5 204 +#define IMX_SC_R_GPIO_6 205 +#define IMX_SC_R_GPIO_7 206 +#define IMX_SC_R_GPT_0 207 +#define IMX_SC_R_GPT_1 208 +#define IMX_SC_R_GPT_2 209 +#define IMX_SC_R_GPT_3 210 +#define IMX_SC_R_GPT_4 211 +#define IMX_SC_R_KPP 212 +#define IMX_SC_R_MU_0A 213 +#define IMX_SC_R_MU_1A 214 +#define IMX_SC_R_MU_2A 215 +#define IMX_SC_R_MU_3A 216 +#define IMX_SC_R_MU_4A 217 +#define IMX_SC_R_MU_5A 218 +#define IMX_SC_R_MU_6A 219 +#define IMX_SC_R_MU_7A 220 +#define IMX_SC_R_MU_8A 221 +#define IMX_SC_R_MU_9A 222 +#define IMX_SC_R_MU_10A 223 +#define IMX_SC_R_MU_11A 224 +#define IMX_SC_R_MU_12A 225 +#define IMX_SC_R_MU_13A 226 +#define IMX_SC_R_MU_5B 227 +#define IMX_SC_R_MU_6B 228 +#define IMX_SC_R_MU_7B 229 +#define IMX_SC_R_MU_8B 230 +#define IMX_SC_R_MU_9B 231 +#define IMX_SC_R_MU_10B 232 +#define IMX_SC_R_MU_11B 233 +#define IMX_SC_R_MU_12B 234 +#define IMX_SC_R_MU_13B 235 +#define IMX_SC_R_ROM_0 236 +#define IMX_SC_R_FSPI_0 237 +#define IMX_SC_R_FSPI_1 238 +#define IMX_SC_R_IEE 239 +#define IMX_SC_R_IEE_R0 240 +#define IMX_SC_R_IEE_R1 241 +#define IMX_SC_R_IEE_R2 242 +#define IMX_SC_R_IEE_R3 243 +#define IMX_SC_R_IEE_R4 244 +#define IMX_SC_R_IEE_R5 245 +#define IMX_SC_R_IEE_R6 246 +#define IMX_SC_R_IEE_R7 247 +#define IMX_SC_R_SDHC_0 248 +#define IMX_SC_R_SDHC_1 249 +#define IMX_SC_R_SDHC_2 250 +#define IMX_SC_R_ENET_0 251 +#define IMX_SC_R_ENET_1 252 +#define IMX_SC_R_MLB_0 253 +#define IMX_SC_R_DMA_2_CH0 254 +#define IMX_SC_R_DMA_2_CH1 255 +#define IMX_SC_R_DMA_2_CH2 256 +#define IMX_SC_R_DMA_2_CH3 257 +#define IMX_SC_R_DMA_2_CH4 258 +#define IMX_SC_R_USB_0 259 +#define IMX_SC_R_USB_1 260 +#define IMX_SC_R_USB_0_PHY 261 +#define IMX_SC_R_USB_2 262 +#define IMX_SC_R_USB_2_PHY 263 +#define IMX_SC_R_DTCP 264 +#define IMX_SC_R_NAND 265 +#define IMX_SC_R_LVDS_0 266 +#define IMX_SC_R_LVDS_0_PWM_0 267 +#define IMX_SC_R_LVDS_0_I2C_0 268 +#define IMX_SC_R_LVDS_0_I2C_1 269 +#define IMX_SC_R_LVDS_1 270 +#define IMX_SC_R_LVDS_1_PWM_0 271 +#define IMX_SC_R_LVDS_1_I2C_0 272 +#define IMX_SC_R_LVDS_1_I2C_1 273 +#define IMX_SC_R_LVDS_2 274 +#define IMX_SC_R_LVDS_2_PWM_0 275 +#define IMX_SC_R_LVDS_2_I2C_0 276 +#define IMX_SC_R_LVDS_2_I2C_1 277 +#define IMX_SC_R_M4_0_PID0 278 +#define IMX_SC_R_M4_0_PID1 279 +#define IMX_SC_R_M4_0_PID2 280 +#define IMX_SC_R_M4_0_PID3 281 +#define IMX_SC_R_M4_0_PID4 282 +#define IMX_SC_R_M4_0_RGPIO 283 +#define IMX_SC_R_M4_0_SEMA42 284 +#define IMX_SC_R_M4_0_TPM 285 +#define IMX_SC_R_M4_0_PIT 286 +#define IMX_SC_R_M4_0_UART 287 +#define IMX_SC_R_M4_0_I2C 288 +#define IMX_SC_R_M4_0_INTMUX 289 +#define IMX_SC_R_M4_0_SIM 290 +#define IMX_SC_R_M4_0_WDOG 291 +#define IMX_SC_R_M4_0_MU_0B 292 +#define IMX_SC_R_M4_0_MU_0A0 293 +#define IMX_SC_R_M4_0_MU_0A1 294 +#define IMX_SC_R_M4_0_MU_0A2 295 +#define IMX_SC_R_M4_0_MU_0A3 296 +#define IMX_SC_R_M4_0_MU_1A 297 +#define IMX_SC_R_M4_1_PID0 298 +#define IMX_SC_R_M4_1_PID1 299 +#define IMX_SC_R_M4_1_PID2 300 +#define IMX_SC_R_M4_1_PID3 301 +#define IMX_SC_R_M4_1_PID4 302 +#define IMX_SC_R_M4_1_RGPIO 303 +#define IMX_SC_R_M4_1_SEMA42 304 +#define IMX_SC_R_M4_1_TPM 305 +#define IMX_SC_R_M4_1_PIT 306 +#define IMX_SC_R_M4_1_UART 307 +#define IMX_SC_R_M4_1_I2C 308 +#define IMX_SC_R_M4_1_INTMUX 309 +#define IMX_SC_R_M4_1_SIM 310 +#define IMX_SC_R_M4_1_WDOG 311 +#define IMX_SC_R_M4_1_MU_0B 312 +#define IMX_SC_R_M4_1_MU_0A0 313 +#define IMX_SC_R_M4_1_MU_0A1 314 +#define IMX_SC_R_M4_1_MU_0A2 315 +#define IMX_SC_R_M4_1_MU_0A3 316 +#define IMX_SC_R_M4_1_MU_1A 317 +#define IMX_SC_R_SAI_0 318 +#define IMX_SC_R_SAI_1 319 +#define IMX_SC_R_SAI_2 320 +#define IMX_SC_R_IRQSTR_SCU2 321 +#define IMX_SC_R_IRQSTR_DSP 322 +#define IMX_SC_R_ELCDIF_PLL 323 +#define IMX_SC_R_UNUSED6 324 +#define IMX_SC_R_AUDIO_PLL_0 325 +#define IMX_SC_R_PI_0 326 +#define IMX_SC_R_PI_0_PWM_0 327 +#define IMX_SC_R_PI_0_PWM_1 328 +#define IMX_SC_R_PI_0_I2C_0 329 +#define IMX_SC_R_PI_0_PLL 330 +#define IMX_SC_R_PI_1 331 +#define IMX_SC_R_PI_1_PWM_0 332 +#define IMX_SC_R_PI_1_PWM_1 333 +#define IMX_SC_R_PI_1_I2C_0 334 +#define IMX_SC_R_PI_1_PLL 335 +#define IMX_SC_R_SC_PID0 336 +#define IMX_SC_R_SC_PID1 337 +#define IMX_SC_R_SC_PID2 338 +#define IMX_SC_R_SC_PID3 339 +#define IMX_SC_R_SC_PID4 340 +#define IMX_SC_R_SC_SEMA42 341 +#define IMX_SC_R_SC_TPM 342 +#define IMX_SC_R_SC_PIT 343 +#define IMX_SC_R_SC_UART 344 +#define IMX_SC_R_SC_I2C 345 +#define IMX_SC_R_SC_MU_0B 346 +#define IMX_SC_R_SC_MU_0A0 347 +#define IMX_SC_R_SC_MU_0A1 348 +#define IMX_SC_R_SC_MU_0A2 349 +#define IMX_SC_R_SC_MU_0A3 350 +#define IMX_SC_R_SC_MU_1A 351 +#define IMX_SC_R_SYSCNT_RD 352 +#define IMX_SC_R_SYSCNT_CMP 353 +#define IMX_SC_R_DEBUG 354 +#define IMX_SC_R_SYSTEM 355 +#define IMX_SC_R_SNVS 356 +#define IMX_SC_R_OTP 357 +#define IMX_SC_R_VPU_PID0 358 +#define IMX_SC_R_VPU_PID1 359 +#define IMX_SC_R_VPU_PID2 360 +#define IMX_SC_R_VPU_PID3 361 +#define IMX_SC_R_VPU_PID4 362 +#define IMX_SC_R_VPU_PID5 363 +#define IMX_SC_R_VPU_PID6 364 +#define IMX_SC_R_VPU_PID7 365 +#define IMX_SC_R_VPU_UART 366 +#define IMX_SC_R_VPUCORE 367 +#define IMX_SC_R_VPUCORE_0 368 +#define IMX_SC_R_VPUCORE_1 369 +#define IMX_SC_R_VPUCORE_2 370 +#define IMX_SC_R_VPUCORE_3 371 +#define IMX_SC_R_DMA_4_CH0 372 +#define IMX_SC_R_DMA_4_CH1 373 +#define IMX_SC_R_DMA_4_CH2 374 +#define IMX_SC_R_DMA_4_CH3 375 +#define IMX_SC_R_DMA_4_CH4 376 +#define IMX_SC_R_ISI_CH0 377 +#define IMX_SC_R_ISI_CH1 378 +#define IMX_SC_R_ISI_CH2 379 +#define IMX_SC_R_ISI_CH3 380 +#define IMX_SC_R_ISI_CH4 381 +#define IMX_SC_R_ISI_CH5 382 +#define IMX_SC_R_ISI_CH6 383 +#define IMX_SC_R_ISI_CH7 384 +#define IMX_SC_R_MJPEG_DEC_S0 385 +#define IMX_SC_R_MJPEG_DEC_S1 386 +#define IMX_SC_R_MJPEG_DEC_S2 387 +#define IMX_SC_R_MJPEG_DEC_S3 388 +#define IMX_SC_R_MJPEG_ENC_S0 389 +#define IMX_SC_R_MJPEG_ENC_S1 390 +#define IMX_SC_R_MJPEG_ENC_S2 391 +#define IMX_SC_R_MJPEG_ENC_S3 392 +#define IMX_SC_R_MIPI_0 393 +#define IMX_SC_R_MIPI_0_PWM_0 394 +#define IMX_SC_R_MIPI_0_I2C_0 395 +#define IMX_SC_R_MIPI_0_I2C_1 396 +#define IMX_SC_R_MIPI_1 397 +#define IMX_SC_R_MIPI_1_PWM_0 398 +#define IMX_SC_R_MIPI_1_I2C_0 399 +#define IMX_SC_R_MIPI_1_I2C_1 400 +#define IMX_SC_R_CSI_0 401 +#define IMX_SC_R_CSI_0_PWM_0 402 +#define IMX_SC_R_CSI_0_I2C_0 403 +#define IMX_SC_R_CSI_1 404 +#define IMX_SC_R_CSI_1_PWM_0 405 +#define IMX_SC_R_CSI_1_I2C_0 406 +#define IMX_SC_R_HDMI 407 +#define IMX_SC_R_HDMI_I2S 408 +#define IMX_SC_R_HDMI_I2C_0 409 +#define IMX_SC_R_HDMI_PLL_0 410 +#define IMX_SC_R_HDMI_RX 411 +#define IMX_SC_R_HDMI_RX_BYPASS 412 +#define IMX_SC_R_HDMI_RX_I2C_0 413 +#define IMX_SC_R_ASRC_0 414 +#define IMX_SC_R_ESAI_0 415 +#define IMX_SC_R_SPDIF_0 416 +#define IMX_SC_R_SPDIF_1 417 +#define IMX_SC_R_SAI_3 418 +#define IMX_SC_R_SAI_4 419 +#define IMX_SC_R_SAI_5 420 +#define IMX_SC_R_GPT_5 421 +#define IMX_SC_R_GPT_6 422 +#define IMX_SC_R_GPT_7 423 +#define IMX_SC_R_GPT_8 424 +#define IMX_SC_R_GPT_9 425 +#define IMX_SC_R_GPT_10 426 +#define IMX_SC_R_DMA_2_CH5 427 +#define IMX_SC_R_DMA_2_CH6 428 +#define IMX_SC_R_DMA_2_CH7 429 +#define IMX_SC_R_DMA_2_CH8 430 +#define IMX_SC_R_DMA_2_CH9 431 +#define IMX_SC_R_DMA_2_CH10 432 +#define IMX_SC_R_DMA_2_CH11 433 +#define IMX_SC_R_DMA_2_CH12 434 +#define IMX_SC_R_DMA_2_CH13 435 +#define IMX_SC_R_DMA_2_CH14 436 +#define IMX_SC_R_DMA_2_CH15 437 +#define IMX_SC_R_DMA_2_CH16 438 +#define IMX_SC_R_DMA_2_CH17 439 +#define IMX_SC_R_DMA_2_CH18 440 +#define IMX_SC_R_DMA_2_CH19 441 +#define IMX_SC_R_DMA_2_CH20 442 +#define IMX_SC_R_DMA_2_CH21 443 +#define IMX_SC_R_DMA_2_CH22 444 +#define IMX_SC_R_DMA_2_CH23 445 +#define IMX_SC_R_DMA_2_CH24 446 +#define IMX_SC_R_DMA_2_CH25 447 +#define IMX_SC_R_DMA_2_CH26 448 +#define IMX_SC_R_DMA_2_CH27 449 +#define IMX_SC_R_DMA_2_CH28 450 +#define IMX_SC_R_DMA_2_CH29 451 +#define IMX_SC_R_DMA_2_CH30 452 +#define IMX_SC_R_DMA_2_CH31 453 +#define IMX_SC_R_ASRC_1 454 +#define IMX_SC_R_ESAI_1 455 +#define IMX_SC_R_SAI_6 456 +#define IMX_SC_R_SAI_7 457 +#define IMX_SC_R_AMIX 458 +#define IMX_SC_R_MQS_0 459 +#define IMX_SC_R_DMA_3_CH0 460 +#define IMX_SC_R_DMA_3_CH1 461 +#define IMX_SC_R_DMA_3_CH2 462 +#define IMX_SC_R_DMA_3_CH3 463 +#define IMX_SC_R_DMA_3_CH4 464 +#define IMX_SC_R_DMA_3_CH5 465 +#define IMX_SC_R_DMA_3_CH6 466 +#define IMX_SC_R_DMA_3_CH7 467 +#define IMX_SC_R_DMA_3_CH8 468 +#define IMX_SC_R_DMA_3_CH9 469 +#define IMX_SC_R_DMA_3_CH10 470 +#define IMX_SC_R_DMA_3_CH11 471 +#define IMX_SC_R_DMA_3_CH12 472 +#define IMX_SC_R_DMA_3_CH13 473 +#define IMX_SC_R_DMA_3_CH14 474 +#define IMX_SC_R_DMA_3_CH15 475 +#define IMX_SC_R_DMA_3_CH16 476 +#define IMX_SC_R_DMA_3_CH17 477 +#define IMX_SC_R_DMA_3_CH18 478 +#define IMX_SC_R_DMA_3_CH19 479 +#define IMX_SC_R_DMA_3_CH20 480 +#define IMX_SC_R_DMA_3_CH21 481 +#define IMX_SC_R_DMA_3_CH22 482 +#define IMX_SC_R_DMA_3_CH23 483 +#define IMX_SC_R_DMA_3_CH24 484 +#define IMX_SC_R_DMA_3_CH25 485 +#define IMX_SC_R_DMA_3_CH26 486 +#define IMX_SC_R_DMA_3_CH27 487 +#define IMX_SC_R_DMA_3_CH28 488 +#define IMX_SC_R_DMA_3_CH29 489 +#define IMX_SC_R_DMA_3_CH30 490 +#define IMX_SC_R_DMA_3_CH31 491 +#define IMX_SC_R_AUDIO_PLL_1 492 +#define IMX_SC_R_AUDIO_CLK_0 493 +#define IMX_SC_R_AUDIO_CLK_1 494 +#define IMX_SC_R_MCLK_OUT_0 495 +#define IMX_SC_R_MCLK_OUT_1 496 +#define IMX_SC_R_PMIC_0 497 +#define IMX_SC_R_PMIC_1 498 +#define IMX_SC_R_SECO 499 +#define IMX_SC_R_CAAM_JR1 500 +#define IMX_SC_R_CAAM_JR2 501 +#define IMX_SC_R_CAAM_JR3 502 +#define IMX_SC_R_SECO_MU_2 503 +#define IMX_SC_R_SECO_MU_3 504 +#define IMX_SC_R_SECO_MU_4 505 +#define IMX_SC_R_HDMI_RX_PWM_0 506 +#define IMX_SC_R_A35 507 +#define IMX_SC_R_A35_0 508 +#define IMX_SC_R_A35_1 509 +#define IMX_SC_R_A35_2 510 +#define IMX_SC_R_A35_3 511 +#define IMX_SC_R_DSP 512 +#define IMX_SC_R_DSP_RAM 513 +#define IMX_SC_R_CAAM_JR1_OUT 514 +#define IMX_SC_R_CAAM_JR2_OUT 515 +#define IMX_SC_R_CAAM_JR3_OUT 516 +#define IMX_SC_R_VPU_DEC_0 517 +#define IMX_SC_R_VPU_ENC_0 518 +#define IMX_SC_R_CAAM_JR0 519 +#define IMX_SC_R_CAAM_JR0_OUT 520 +#define IMX_SC_R_PMIC_2 521 +#define IMX_SC_R_DBLOGIC 522 +#define IMX_SC_R_HDMI_PLL_1 523 +#define IMX_SC_R_BOARD_R0 524 +#define IMX_SC_R_BOARD_R1 525 +#define IMX_SC_R_BOARD_R2 526 +#define IMX_SC_R_BOARD_R3 527 +#define IMX_SC_R_BOARD_R4 528 +#define IMX_SC_R_BOARD_R5 529 +#define IMX_SC_R_BOARD_R6 530 +#define IMX_SC_R_BOARD_R7 531 +#define IMX_SC_R_MJPEG_DEC_MP 532 +#define IMX_SC_R_MJPEG_ENC_MP 533 +#define IMX_SC_R_VPU_TS_0 534 +#define IMX_SC_R_VPU_MU_0 535 +#define IMX_SC_R_VPU_MU_1 536 +#define IMX_SC_R_VPU_MU_2 537 +#define IMX_SC_R_VPU_MU_3 538 +#define IMX_SC_R_VPU_ENC_1 539 +#define IMX_SC_R_VPU 540 +#define IMX_SC_R_LAST 541 + +#endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h new file mode 100644 index 000000000000..8a513bd9166e --- /dev/null +++ b/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index bf54779d1625..85cc5f23cf9f 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -16,13 +16,12 @@ #define R8A77970_PD_CA53_CPU0 5 #define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CR7 13 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A3IR 24 #define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2IR2 28 -#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 #define R8A77970_PD_A2SC0 30 #define R8A77970_PD_A2SC1 31 diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h index 2c90c1237725..e12c8587b87e 100644 --- a/include/dt-bindings/power/r8a77980-sysc.h +++ b/include/dt-bindings/power/r8a77980-sysc.h @@ -15,14 +15,14 @@ #define R8A77980_PD_A2SC2 0 #define R8A77980_PD_A2SC3 1 #define R8A77980_PD_A2SC4 2 -#define R8A77980_PD_A2PD0 3 -#define R8A77980_PD_A2PD1 4 +#define R8A77980_PD_A2DP0 3 +#define R8A77980_PD_A2DP1 4 #define R8A77980_PD_CA53_CPU0 5 #define R8A77980_PD_CA53_CPU1 6 #define R8A77980_PD_CA53_CPU2 7 #define R8A77980_PD_CA53_CPU3 8 #define R8A77980_PD_A2CN 10 -#define R8A77980_PD_A3VIP 11 +#define R8A77980_PD_A3VIP0 11 #define R8A77980_PD_A2IR5 12 #define R8A77980_PD_CR7 13 #define R8A77980_PD_A2IR4 15 diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h index b3ff8e09a78f..3575f9f4b0bd 100644 --- a/include/dt-bindings/power/raspberrypi-power.h +++ b/include/dt-bindings/power/raspberrypi-power.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 000000000000..acf9f310ac53 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO 6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 000000000000..93d23dfba33f --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__ + +/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3188_PD_RTC 12 + +#endif diff --git a/include/linux/dma/pxa-dma.h b/include/linux/dma/pxa-dma.h index 9fc594f69eff..fceb5df07097 100644 --- a/include/linux/dma/pxa-dma.h +++ b/include/linux/dma/pxa-dma.h @@ -23,15 +23,4 @@ struct pxad_param { enum pxad_chan_prio prio; }; -struct dma_chan; - -#ifdef CONFIG_PXA_DMA -bool pxad_filter_fn(struct dma_chan *chan, void *param); -#else -static inline bool pxad_filter_fn(struct dma_chan *chan, void *param) -{ - return false; -} -#endif - #endif /* _PXA_DMA_H_ */ diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h index 29ada609de03..ebc55098faee 100644 --- a/include/linux/firmware/imx/sci.h +++ b/include/linux/firmware/imx/sci.h @@ -14,4 +14,5 @@ #include <linux/firmware/imx/types.h> #include <linux/firmware/imx/svc/misc.h> +#include <linux/firmware/imx/svc/pm.h> #endif /* _SC_SCI_H */ diff --git a/include/linux/firmware/imx/svc/pm.h b/include/linux/firmware/imx/svc/pm.h new file mode 100644 index 000000000000..1f6975dd37b0 --- /dev/null +++ b/include/linux/firmware/imx/svc/pm.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * PM_SVC (SVC) Power Management Service + * + * Module for the Power Management (PM) service. + */ + +#ifndef _SC_PM_API_H +#define _SC_PM_API_H + +#include <linux/firmware/imx/sci.h> + +/* + * This type is used to indicate RPC PM function calls. + */ +enum imx_sc_pm_func { + IMX_SC_PM_FUNC_UNKNOWN = 0, + IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19, + IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1, + IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2, + IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3, + IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4, + IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16, + IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17, + IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, + IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5, + IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6, + IMX_SC_PM_FUNC_CLOCK_ENABLE = 7, + IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14, + IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15, + IMX_SC_PM_FUNC_RESET = 13, + IMX_SC_PM_FUNC_RESET_REASON = 10, + IMX_SC_PM_FUNC_BOOT = 8, + IMX_SC_PM_FUNC_REBOOT = 9, + IMX_SC_PM_FUNC_REBOOT_PARTITION = 12, + IMX_SC_PM_FUNC_CPU_START = 11, +}; + +/* + * Defines for ALL parameters + */ +#define IMX_SC_PM_CLK_ALL UINT8_MAX /* All clocks */ + +/* + * Defines for SC PM Power Mode + */ +#define IMX_SC_PM_PW_MODE_OFF 0 /* Power off */ +#define IMX_SC_PM_PW_MODE_STBY 1 /* Power in standby */ +#define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */ +#define IMX_SC_PM_PW_MODE_ON 3 /* Power on */ + +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + +/* + * Defines for SC PM CLK Parent + */ +#define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */ +#define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */ +#define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */ +#define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */ +#define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */ + +#endif /* _SC_PM_API_H */ diff --git a/include/linux/firmware/imx/types.h b/include/linux/firmware/imx/types.h index 9cbf0c4a6069..80821100e85f 100644 --- a/include/linux/firmware/imx/types.h +++ b/include/linux/firmware/imx/types.h @@ -10,558 +10,6 @@ #define _SC_TYPES_H /* - * This type is used to indicate a resource. Resources include peripherals - * and bus masters (but not memory regions). Note items from list should - * never be changed or removed (only added to at the end of the list). - */ -enum imx_sc_rsrc { - IMX_SC_R_A53 = 0, - IMX_SC_R_A53_0 = 1, - IMX_SC_R_A53_1 = 2, - IMX_SC_R_A53_2 = 3, - IMX_SC_R_A53_3 = 4, - IMX_SC_R_A72 = 5, - IMX_SC_R_A72_0 = 6, - IMX_SC_R_A72_1 = 7, - IMX_SC_R_A72_2 = 8, - IMX_SC_R_A72_3 = 9, - IMX_SC_R_CCI = 10, - IMX_SC_R_DB = 11, - IMX_SC_R_DRC_0 = 12, - IMX_SC_R_DRC_1 = 13, - IMX_SC_R_GIC_SMMU = 14, - IMX_SC_R_IRQSTR_M4_0 = 15, - IMX_SC_R_IRQSTR_M4_1 = 16, - IMX_SC_R_SMMU = 17, - IMX_SC_R_GIC = 18, - IMX_SC_R_DC_0_BLIT0 = 19, - IMX_SC_R_DC_0_BLIT1 = 20, - IMX_SC_R_DC_0_BLIT2 = 21, - IMX_SC_R_DC_0_BLIT_OUT = 22, - IMX_SC_R_DC_0_CAPTURE0 = 23, - IMX_SC_R_DC_0_CAPTURE1 = 24, - IMX_SC_R_DC_0_WARP = 25, - IMX_SC_R_DC_0_INTEGRAL0 = 26, - IMX_SC_R_DC_0_INTEGRAL1 = 27, - IMX_SC_R_DC_0_VIDEO0 = 28, - IMX_SC_R_DC_0_VIDEO1 = 29, - IMX_SC_R_DC_0_FRAC0 = 30, - IMX_SC_R_DC_0_FRAC1 = 31, - IMX_SC_R_DC_0 = 32, - IMX_SC_R_GPU_2_PID0 = 33, - IMX_SC_R_DC_0_PLL_0 = 34, - IMX_SC_R_DC_0_PLL_1 = 35, - IMX_SC_R_DC_1_BLIT0 = 36, - IMX_SC_R_DC_1_BLIT1 = 37, - IMX_SC_R_DC_1_BLIT2 = 38, - IMX_SC_R_DC_1_BLIT_OUT = 39, - IMX_SC_R_DC_1_CAPTURE0 = 40, - IMX_SC_R_DC_1_CAPTURE1 = 41, - IMX_SC_R_DC_1_WARP = 42, - IMX_SC_R_DC_1_INTEGRAL0 = 43, - IMX_SC_R_DC_1_INTEGRAL1 = 44, - IMX_SC_R_DC_1_VIDEO0 = 45, - IMX_SC_R_DC_1_VIDEO1 = 46, - IMX_SC_R_DC_1_FRAC0 = 47, - IMX_SC_R_DC_1_FRAC1 = 48, - IMX_SC_R_DC_1 = 49, - IMX_SC_R_GPU_3_PID0 = 50, - IMX_SC_R_DC_1_PLL_0 = 51, - IMX_SC_R_DC_1_PLL_1 = 52, - IMX_SC_R_SPI_0 = 53, - IMX_SC_R_SPI_1 = 54, - IMX_SC_R_SPI_2 = 55, - IMX_SC_R_SPI_3 = 56, - IMX_SC_R_UART_0 = 57, - IMX_SC_R_UART_1 = 58, - IMX_SC_R_UART_2 = 59, - IMX_SC_R_UART_3 = 60, - IMX_SC_R_UART_4 = 61, - IMX_SC_R_EMVSIM_0 = 62, - IMX_SC_R_EMVSIM_1 = 63, - IMX_SC_R_DMA_0_CH0 = 64, - IMX_SC_R_DMA_0_CH1 = 65, - IMX_SC_R_DMA_0_CH2 = 66, - IMX_SC_R_DMA_0_CH3 = 67, - IMX_SC_R_DMA_0_CH4 = 68, - IMX_SC_R_DMA_0_CH5 = 69, - IMX_SC_R_DMA_0_CH6 = 70, - IMX_SC_R_DMA_0_CH7 = 71, - IMX_SC_R_DMA_0_CH8 = 72, - IMX_SC_R_DMA_0_CH9 = 73, - IMX_SC_R_DMA_0_CH10 = 74, - IMX_SC_R_DMA_0_CH11 = 75, - IMX_SC_R_DMA_0_CH12 = 76, - IMX_SC_R_DMA_0_CH13 = 77, - IMX_SC_R_DMA_0_CH14 = 78, - IMX_SC_R_DMA_0_CH15 = 79, - IMX_SC_R_DMA_0_CH16 = 80, - IMX_SC_R_DMA_0_CH17 = 81, - IMX_SC_R_DMA_0_CH18 = 82, - IMX_SC_R_DMA_0_CH19 = 83, - IMX_SC_R_DMA_0_CH20 = 84, - IMX_SC_R_DMA_0_CH21 = 85, - IMX_SC_R_DMA_0_CH22 = 86, - IMX_SC_R_DMA_0_CH23 = 87, - IMX_SC_R_DMA_0_CH24 = 88, - IMX_SC_R_DMA_0_CH25 = 89, - IMX_SC_R_DMA_0_CH26 = 90, - IMX_SC_R_DMA_0_CH27 = 91, - IMX_SC_R_DMA_0_CH28 = 92, - IMX_SC_R_DMA_0_CH29 = 93, - IMX_SC_R_DMA_0_CH30 = 94, - IMX_SC_R_DMA_0_CH31 = 95, - IMX_SC_R_I2C_0 = 96, - IMX_SC_R_I2C_1 = 97, - IMX_SC_R_I2C_2 = 98, - IMX_SC_R_I2C_3 = 99, - IMX_SC_R_I2C_4 = 100, - IMX_SC_R_ADC_0 = 101, - IMX_SC_R_ADC_1 = 102, - IMX_SC_R_FTM_0 = 103, - IMX_SC_R_FTM_1 = 104, - IMX_SC_R_CAN_0 = 105, - IMX_SC_R_CAN_1 = 106, - IMX_SC_R_CAN_2 = 107, - IMX_SC_R_DMA_1_CH0 = 108, - IMX_SC_R_DMA_1_CH1 = 109, - IMX_SC_R_DMA_1_CH2 = 110, - IMX_SC_R_DMA_1_CH3 = 111, - IMX_SC_R_DMA_1_CH4 = 112, - IMX_SC_R_DMA_1_CH5 = 113, - IMX_SC_R_DMA_1_CH6 = 114, - IMX_SC_R_DMA_1_CH7 = 115, - IMX_SC_R_DMA_1_CH8 = 116, - IMX_SC_R_DMA_1_CH9 = 117, - IMX_SC_R_DMA_1_CH10 = 118, - IMX_SC_R_DMA_1_CH11 = 119, - IMX_SC_R_DMA_1_CH12 = 120, - IMX_SC_R_DMA_1_CH13 = 121, - IMX_SC_R_DMA_1_CH14 = 122, - IMX_SC_R_DMA_1_CH15 = 123, - IMX_SC_R_DMA_1_CH16 = 124, - IMX_SC_R_DMA_1_CH17 = 125, - IMX_SC_R_DMA_1_CH18 = 126, - IMX_SC_R_DMA_1_CH19 = 127, - IMX_SC_R_DMA_1_CH20 = 128, - IMX_SC_R_DMA_1_CH21 = 129, - IMX_SC_R_DMA_1_CH22 = 130, - IMX_SC_R_DMA_1_CH23 = 131, - IMX_SC_R_DMA_1_CH24 = 132, - IMX_SC_R_DMA_1_CH25 = 133, - IMX_SC_R_DMA_1_CH26 = 134, - IMX_SC_R_DMA_1_CH27 = 135, - IMX_SC_R_DMA_1_CH28 = 136, - IMX_SC_R_DMA_1_CH29 = 137, - IMX_SC_R_DMA_1_CH30 = 138, - IMX_SC_R_DMA_1_CH31 = 139, - IMX_SC_R_UNUSED1 = 140, - IMX_SC_R_UNUSED2 = 141, - IMX_SC_R_UNUSED3 = 142, - IMX_SC_R_UNUSED4 = 143, - IMX_SC_R_GPU_0_PID0 = 144, - IMX_SC_R_GPU_0_PID1 = 145, - IMX_SC_R_GPU_0_PID2 = 146, - IMX_SC_R_GPU_0_PID3 = 147, - IMX_SC_R_GPU_1_PID0 = 148, - IMX_SC_R_GPU_1_PID1 = 149, - IMX_SC_R_GPU_1_PID2 = 150, - IMX_SC_R_GPU_1_PID3 = 151, - IMX_SC_R_PCIE_A = 152, - IMX_SC_R_SERDES_0 = 153, - IMX_SC_R_MATCH_0 = 154, - IMX_SC_R_MATCH_1 = 155, - IMX_SC_R_MATCH_2 = 156, - IMX_SC_R_MATCH_3 = 157, - IMX_SC_R_MATCH_4 = 158, - IMX_SC_R_MATCH_5 = 159, - IMX_SC_R_MATCH_6 = 160, - IMX_SC_R_MATCH_7 = 161, - IMX_SC_R_MATCH_8 = 162, - IMX_SC_R_MATCH_9 = 163, - IMX_SC_R_MATCH_10 = 164, - IMX_SC_R_MATCH_11 = 165, - IMX_SC_R_MATCH_12 = 166, - IMX_SC_R_MATCH_13 = 167, - IMX_SC_R_MATCH_14 = 168, - IMX_SC_R_PCIE_B = 169, - IMX_SC_R_SATA_0 = 170, - IMX_SC_R_SERDES_1 = 171, - IMX_SC_R_HSIO_GPIO = 172, - IMX_SC_R_MATCH_15 = 173, - IMX_SC_R_MATCH_16 = 174, - IMX_SC_R_MATCH_17 = 175, - IMX_SC_R_MATCH_18 = 176, - IMX_SC_R_MATCH_19 = 177, - IMX_SC_R_MATCH_20 = 178, - IMX_SC_R_MATCH_21 = 179, - IMX_SC_R_MATCH_22 = 180, - IMX_SC_R_MATCH_23 = 181, - IMX_SC_R_MATCH_24 = 182, - IMX_SC_R_MATCH_25 = 183, - IMX_SC_R_MATCH_26 = 184, - IMX_SC_R_MATCH_27 = 185, - IMX_SC_R_MATCH_28 = 186, - IMX_SC_R_LCD_0 = 187, - IMX_SC_R_LCD_0_PWM_0 = 188, - IMX_SC_R_LCD_0_I2C_0 = 189, - IMX_SC_R_LCD_0_I2C_1 = 190, - IMX_SC_R_PWM_0 = 191, - IMX_SC_R_PWM_1 = 192, - IMX_SC_R_PWM_2 = 193, - IMX_SC_R_PWM_3 = 194, - IMX_SC_R_PWM_4 = 195, - IMX_SC_R_PWM_5 = 196, - IMX_SC_R_PWM_6 = 197, - IMX_SC_R_PWM_7 = 198, - IMX_SC_R_GPIO_0 = 199, - IMX_SC_R_GPIO_1 = 200, - IMX_SC_R_GPIO_2 = 201, - IMX_SC_R_GPIO_3 = 202, - IMX_SC_R_GPIO_4 = 203, - IMX_SC_R_GPIO_5 = 204, - IMX_SC_R_GPIO_6 = 205, - IMX_SC_R_GPIO_7 = 206, - IMX_SC_R_GPT_0 = 207, - IMX_SC_R_GPT_1 = 208, - IMX_SC_R_GPT_2 = 209, - IMX_SC_R_GPT_3 = 210, - IMX_SC_R_GPT_4 = 211, - IMX_SC_R_KPP = 212, - IMX_SC_R_MU_0A = 213, - IMX_SC_R_MU_1A = 214, - IMX_SC_R_MU_2A = 215, - IMX_SC_R_MU_3A = 216, - IMX_SC_R_MU_4A = 217, - IMX_SC_R_MU_5A = 218, - IMX_SC_R_MU_6A = 219, - IMX_SC_R_MU_7A = 220, - IMX_SC_R_MU_8A = 221, - IMX_SC_R_MU_9A = 222, - IMX_SC_R_MU_10A = 223, - IMX_SC_R_MU_11A = 224, - IMX_SC_R_MU_12A = 225, - IMX_SC_R_MU_13A = 226, - IMX_SC_R_MU_5B = 227, - IMX_SC_R_MU_6B = 228, - IMX_SC_R_MU_7B = 229, - IMX_SC_R_MU_8B = 230, - IMX_SC_R_MU_9B = 231, - IMX_SC_R_MU_10B = 232, - IMX_SC_R_MU_11B = 233, - IMX_SC_R_MU_12B = 234, - IMX_SC_R_MU_13B = 235, - IMX_SC_R_ROM_0 = 236, - IMX_SC_R_FSPI_0 = 237, - IMX_SC_R_FSPI_1 = 238, - IMX_SC_R_IEE = 239, - IMX_SC_R_IEE_R0 = 240, - IMX_SC_R_IEE_R1 = 241, - IMX_SC_R_IEE_R2 = 242, - IMX_SC_R_IEE_R3 = 243, - IMX_SC_R_IEE_R4 = 244, - IMX_SC_R_IEE_R5 = 245, - IMX_SC_R_IEE_R6 = 246, - IMX_SC_R_IEE_R7 = 247, - IMX_SC_R_SDHC_0 = 248, - IMX_SC_R_SDHC_1 = 249, - IMX_SC_R_SDHC_2 = 250, - IMX_SC_R_ENET_0 = 251, - IMX_SC_R_ENET_1 = 252, - IMX_SC_R_MLB_0 = 253, - IMX_SC_R_DMA_2_CH0 = 254, - IMX_SC_R_DMA_2_CH1 = 255, - IMX_SC_R_DMA_2_CH2 = 256, - IMX_SC_R_DMA_2_CH3 = 257, - IMX_SC_R_DMA_2_CH4 = 258, - IMX_SC_R_USB_0 = 259, - IMX_SC_R_USB_1 = 260, - IMX_SC_R_USB_0_PHY = 261, - IMX_SC_R_USB_2 = 262, - IMX_SC_R_USB_2_PHY = 263, - IMX_SC_R_DTCP = 264, - IMX_SC_R_NAND = 265, - IMX_SC_R_LVDS_0 = 266, - IMX_SC_R_LVDS_0_PWM_0 = 267, - IMX_SC_R_LVDS_0_I2C_0 = 268, - IMX_SC_R_LVDS_0_I2C_1 = 269, - IMX_SC_R_LVDS_1 = 270, - IMX_SC_R_LVDS_1_PWM_0 = 271, - IMX_SC_R_LVDS_1_I2C_0 = 272, - IMX_SC_R_LVDS_1_I2C_1 = 273, - IMX_SC_R_LVDS_2 = 274, - IMX_SC_R_LVDS_2_PWM_0 = 275, - IMX_SC_R_LVDS_2_I2C_0 = 276, - IMX_SC_R_LVDS_2_I2C_1 = 277, - IMX_SC_R_M4_0_PID0 = 278, - IMX_SC_R_M4_0_PID1 = 279, - IMX_SC_R_M4_0_PID2 = 280, - IMX_SC_R_M4_0_PID3 = 281, - IMX_SC_R_M4_0_PID4 = 282, - IMX_SC_R_M4_0_RGPIO = 283, - IMX_SC_R_M4_0_SEMA42 = 284, - IMX_SC_R_M4_0_TPM = 285, - IMX_SC_R_M4_0_PIT = 286, - IMX_SC_R_M4_0_UART = 287, - IMX_SC_R_M4_0_I2C = 288, - IMX_SC_R_M4_0_INTMUX = 289, - IMX_SC_R_M4_0_SIM = 290, - IMX_SC_R_M4_0_WDOG = 291, - IMX_SC_R_M4_0_MU_0B = 292, - IMX_SC_R_M4_0_MU_0A0 = 293, - IMX_SC_R_M4_0_MU_0A1 = 294, - IMX_SC_R_M4_0_MU_0A2 = 295, - IMX_SC_R_M4_0_MU_0A3 = 296, - IMX_SC_R_M4_0_MU_1A = 297, - IMX_SC_R_M4_1_PID0 = 298, - IMX_SC_R_M4_1_PID1 = 299, - IMX_SC_R_M4_1_PID2 = 300, - IMX_SC_R_M4_1_PID3 = 301, - IMX_SC_R_M4_1_PID4 = 302, - IMX_SC_R_M4_1_RGPIO = 303, - IMX_SC_R_M4_1_SEMA42 = 304, - IMX_SC_R_M4_1_TPM = 305, - IMX_SC_R_M4_1_PIT = 306, - IMX_SC_R_M4_1_UART = 307, - IMX_SC_R_M4_1_I2C = 308, - IMX_SC_R_M4_1_INTMUX = 309, - IMX_SC_R_M4_1_SIM = 310, - IMX_SC_R_M4_1_WDOG = 311, - IMX_SC_R_M4_1_MU_0B = 312, - IMX_SC_R_M4_1_MU_0A0 = 313, - IMX_SC_R_M4_1_MU_0A1 = 314, - IMX_SC_R_M4_1_MU_0A2 = 315, - IMX_SC_R_M4_1_MU_0A3 = 316, - IMX_SC_R_M4_1_MU_1A = 317, - IMX_SC_R_SAI_0 = 318, - IMX_SC_R_SAI_1 = 319, - IMX_SC_R_SAI_2 = 320, - IMX_SC_R_IRQSTR_SCU2 = 321, - IMX_SC_R_IRQSTR_DSP = 322, - IMX_SC_R_UNUSED5 = 323, - IMX_SC_R_UNUSED6 = 324, - IMX_SC_R_AUDIO_PLL_0 = 325, - IMX_SC_R_PI_0 = 326, - IMX_SC_R_PI_0_PWM_0 = 327, - IMX_SC_R_PI_0_PWM_1 = 328, - IMX_SC_R_PI_0_I2C_0 = 329, - IMX_SC_R_PI_0_PLL = 330, - IMX_SC_R_PI_1 = 331, - IMX_SC_R_PI_1_PWM_0 = 332, - IMX_SC_R_PI_1_PWM_1 = 333, - IMX_SC_R_PI_1_I2C_0 = 334, - IMX_SC_R_PI_1_PLL = 335, - IMX_SC_R_SC_PID0 = 336, - IMX_SC_R_SC_PID1 = 337, - IMX_SC_R_SC_PID2 = 338, - IMX_SC_R_SC_PID3 = 339, - IMX_SC_R_SC_PID4 = 340, - IMX_SC_R_SC_SEMA42 = 341, - IMX_SC_R_SC_TPM = 342, - IMX_SC_R_SC_PIT = 343, - IMX_SC_R_SC_UART = 344, - IMX_SC_R_SC_I2C = 345, - IMX_SC_R_SC_MU_0B = 346, - IMX_SC_R_SC_MU_0A0 = 347, - IMX_SC_R_SC_MU_0A1 = 348, - IMX_SC_R_SC_MU_0A2 = 349, - IMX_SC_R_SC_MU_0A3 = 350, - IMX_SC_R_SC_MU_1A = 351, - IMX_SC_R_SYSCNT_RD = 352, - IMX_SC_R_SYSCNT_CMP = 353, - IMX_SC_R_DEBUG = 354, - IMX_SC_R_SYSTEM = 355, - IMX_SC_R_SNVS = 356, - IMX_SC_R_OTP = 357, - IMX_SC_R_VPU_PID0 = 358, - IMX_SC_R_VPU_PID1 = 359, - IMX_SC_R_VPU_PID2 = 360, - IMX_SC_R_VPU_PID3 = 361, - IMX_SC_R_VPU_PID4 = 362, - IMX_SC_R_VPU_PID5 = 363, - IMX_SC_R_VPU_PID6 = 364, - IMX_SC_R_VPU_PID7 = 365, - IMX_SC_R_VPU_UART = 366, - IMX_SC_R_VPUCORE = 367, - IMX_SC_R_VPUCORE_0 = 368, - IMX_SC_R_VPUCORE_1 = 369, - IMX_SC_R_VPUCORE_2 = 370, - IMX_SC_R_VPUCORE_3 = 371, - IMX_SC_R_DMA_4_CH0 = 372, - IMX_SC_R_DMA_4_CH1 = 373, - IMX_SC_R_DMA_4_CH2 = 374, - IMX_SC_R_DMA_4_CH3 = 375, - IMX_SC_R_DMA_4_CH4 = 376, - IMX_SC_R_ISI_CH0 = 377, - IMX_SC_R_ISI_CH1 = 378, - IMX_SC_R_ISI_CH2 = 379, - IMX_SC_R_ISI_CH3 = 380, - IMX_SC_R_ISI_CH4 = 381, - IMX_SC_R_ISI_CH5 = 382, - IMX_SC_R_ISI_CH6 = 383, - IMX_SC_R_ISI_CH7 = 384, - IMX_SC_R_MJPEG_DEC_S0 = 385, - IMX_SC_R_MJPEG_DEC_S1 = 386, - IMX_SC_R_MJPEG_DEC_S2 = 387, - IMX_SC_R_MJPEG_DEC_S3 = 388, - IMX_SC_R_MJPEG_ENC_S0 = 389, - IMX_SC_R_MJPEG_ENC_S1 = 390, - IMX_SC_R_MJPEG_ENC_S2 = 391, - IMX_SC_R_MJPEG_ENC_S3 = 392, - IMX_SC_R_MIPI_0 = 393, - IMX_SC_R_MIPI_0_PWM_0 = 394, - IMX_SC_R_MIPI_0_I2C_0 = 395, - IMX_SC_R_MIPI_0_I2C_1 = 396, - IMX_SC_R_MIPI_1 = 397, - IMX_SC_R_MIPI_1_PWM_0 = 398, - IMX_SC_R_MIPI_1_I2C_0 = 399, - IMX_SC_R_MIPI_1_I2C_1 = 400, - IMX_SC_R_CSI_0 = 401, - IMX_SC_R_CSI_0_PWM_0 = 402, - IMX_SC_R_CSI_0_I2C_0 = 403, - IMX_SC_R_CSI_1 = 404, - IMX_SC_R_CSI_1_PWM_0 = 405, - IMX_SC_R_CSI_1_I2C_0 = 406, - IMX_SC_R_HDMI = 407, - IMX_SC_R_HDMI_I2S = 408, - IMX_SC_R_HDMI_I2C_0 = 409, - IMX_SC_R_HDMI_PLL_0 = 410, - IMX_SC_R_HDMI_RX = 411, - IMX_SC_R_HDMI_RX_BYPASS = 412, - IMX_SC_R_HDMI_RX_I2C_0 = 413, - IMX_SC_R_ASRC_0 = 414, - IMX_SC_R_ESAI_0 = 415, - IMX_SC_R_SPDIF_0 = 416, - IMX_SC_R_SPDIF_1 = 417, - IMX_SC_R_SAI_3 = 418, - IMX_SC_R_SAI_4 = 419, - IMX_SC_R_SAI_5 = 420, - IMX_SC_R_GPT_5 = 421, - IMX_SC_R_GPT_6 = 422, - IMX_SC_R_GPT_7 = 423, - IMX_SC_R_GPT_8 = 424, - IMX_SC_R_GPT_9 = 425, - IMX_SC_R_GPT_10 = 426, - IMX_SC_R_DMA_2_CH5 = 427, - IMX_SC_R_DMA_2_CH6 = 428, - IMX_SC_R_DMA_2_CH7 = 429, - IMX_SC_R_DMA_2_CH8 = 430, - IMX_SC_R_DMA_2_CH9 = 431, - IMX_SC_R_DMA_2_CH10 = 432, - IMX_SC_R_DMA_2_CH11 = 433, - IMX_SC_R_DMA_2_CH12 = 434, - IMX_SC_R_DMA_2_CH13 = 435, - IMX_SC_R_DMA_2_CH14 = 436, - IMX_SC_R_DMA_2_CH15 = 437, - IMX_SC_R_DMA_2_CH16 = 438, - IMX_SC_R_DMA_2_CH17 = 439, - IMX_SC_R_DMA_2_CH18 = 440, - IMX_SC_R_DMA_2_CH19 = 441, - IMX_SC_R_DMA_2_CH20 = 442, - IMX_SC_R_DMA_2_CH21 = 443, - IMX_SC_R_DMA_2_CH22 = 444, - IMX_SC_R_DMA_2_CH23 = 445, - IMX_SC_R_DMA_2_CH24 = 446, - IMX_SC_R_DMA_2_CH25 = 447, - IMX_SC_R_DMA_2_CH26 = 448, - IMX_SC_R_DMA_2_CH27 = 449, - IMX_SC_R_DMA_2_CH28 = 450, - IMX_SC_R_DMA_2_CH29 = 451, - IMX_SC_R_DMA_2_CH30 = 452, - IMX_SC_R_DMA_2_CH31 = 453, - IMX_SC_R_ASRC_1 = 454, - IMX_SC_R_ESAI_1 = 455, - IMX_SC_R_SAI_6 = 456, - IMX_SC_R_SAI_7 = 457, - IMX_SC_R_AMIX = 458, - IMX_SC_R_MQS_0 = 459, - IMX_SC_R_DMA_3_CH0 = 460, - IMX_SC_R_DMA_3_CH1 = 461, - IMX_SC_R_DMA_3_CH2 = 462, - IMX_SC_R_DMA_3_CH3 = 463, - IMX_SC_R_DMA_3_CH4 = 464, - IMX_SC_R_DMA_3_CH5 = 465, - IMX_SC_R_DMA_3_CH6 = 466, - IMX_SC_R_DMA_3_CH7 = 467, - IMX_SC_R_DMA_3_CH8 = 468, - IMX_SC_R_DMA_3_CH9 = 469, - IMX_SC_R_DMA_3_CH10 = 470, - IMX_SC_R_DMA_3_CH11 = 471, - IMX_SC_R_DMA_3_CH12 = 472, - IMX_SC_R_DMA_3_CH13 = 473, - IMX_SC_R_DMA_3_CH14 = 474, - IMX_SC_R_DMA_3_CH15 = 475, - IMX_SC_R_DMA_3_CH16 = 476, - IMX_SC_R_DMA_3_CH17 = 477, - IMX_SC_R_DMA_3_CH18 = 478, - IMX_SC_R_DMA_3_CH19 = 479, - IMX_SC_R_DMA_3_CH20 = 480, - IMX_SC_R_DMA_3_CH21 = 481, - IMX_SC_R_DMA_3_CH22 = 482, - IMX_SC_R_DMA_3_CH23 = 483, - IMX_SC_R_DMA_3_CH24 = 484, - IMX_SC_R_DMA_3_CH25 = 485, - IMX_SC_R_DMA_3_CH26 = 486, - IMX_SC_R_DMA_3_CH27 = 487, - IMX_SC_R_DMA_3_CH28 = 488, - IMX_SC_R_DMA_3_CH29 = 489, - IMX_SC_R_DMA_3_CH30 = 490, - IMX_SC_R_DMA_3_CH31 = 491, - IMX_SC_R_AUDIO_PLL_1 = 492, - IMX_SC_R_AUDIO_CLK_0 = 493, - IMX_SC_R_AUDIO_CLK_1 = 494, - IMX_SC_R_MCLK_OUT_0 = 495, - IMX_SC_R_MCLK_OUT_1 = 496, - IMX_SC_R_PMIC_0 = 497, - IMX_SC_R_PMIC_1 = 498, - IMX_SC_R_SECO = 499, - IMX_SC_R_CAAM_JR1 = 500, - IMX_SC_R_CAAM_JR2 = 501, - IMX_SC_R_CAAM_JR3 = 502, - IMX_SC_R_SECO_MU_2 = 503, - IMX_SC_R_SECO_MU_3 = 504, - IMX_SC_R_SECO_MU_4 = 505, - IMX_SC_R_HDMI_RX_PWM_0 = 506, - IMX_SC_R_A35 = 507, - IMX_SC_R_A35_0 = 508, - IMX_SC_R_A35_1 = 509, - IMX_SC_R_A35_2 = 510, - IMX_SC_R_A35_3 = 511, - IMX_SC_R_DSP = 512, - IMX_SC_R_DSP_RAM = 513, - IMX_SC_R_CAAM_JR1_OUT = 514, - IMX_SC_R_CAAM_JR2_OUT = 515, - IMX_SC_R_CAAM_JR3_OUT = 516, - IMX_SC_R_VPU_DEC_0 = 517, - IMX_SC_R_VPU_ENC_0 = 518, - IMX_SC_R_CAAM_JR0 = 519, - IMX_SC_R_CAAM_JR0_OUT = 520, - IMX_SC_R_PMIC_2 = 521, - IMX_SC_R_DBLOGIC = 522, - IMX_SC_R_HDMI_PLL_1 = 523, - IMX_SC_R_BOARD_R0 = 524, - IMX_SC_R_BOARD_R1 = 525, - IMX_SC_R_BOARD_R2 = 526, - IMX_SC_R_BOARD_R3 = 527, - IMX_SC_R_BOARD_R4 = 528, - IMX_SC_R_BOARD_R5 = 529, - IMX_SC_R_BOARD_R6 = 530, - IMX_SC_R_BOARD_R7 = 531, - IMX_SC_R_MJPEG_DEC_MP = 532, - IMX_SC_R_MJPEG_ENC_MP = 533, - IMX_SC_R_VPU_TS_0 = 534, - IMX_SC_R_VPU_MU_0 = 535, - IMX_SC_R_VPU_MU_1 = 536, - IMX_SC_R_VPU_MU_2 = 537, - IMX_SC_R_VPU_MU_3 = 538, - IMX_SC_R_VPU_ENC_1 = 539, - IMX_SC_R_VPU = 540, - IMX_SC_R_LAST -}; - -/* NOTE - please add by replacing some of the UNUSED from above! */ - -/* * This type is used to indicate a control. */ enum imx_sc_ctrl { diff --git a/include/linux/pl353-smc.h b/include/linux/pl353-smc.h new file mode 100644 index 000000000000..0e0d3df9bf72 --- /dev/null +++ b/include/linux/pl353-smc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ARM PL353 SMC Driver Header + * + * Copyright (C) 2012 - 2018 Xilinx, Inc + */ + +#ifndef __LINUX_PL353_SMC_H +#define __LINUX_PL353_SMC_H + +enum pl353_smc_ecc_mode { + PL353_SMC_ECCMODE_BYPASS = 0, + PL353_SMC_ECCMODE_APB = 1, + PL353_SMC_ECCMODE_MEM = 2 +}; + +enum pl353_smc_mem_width { + PL353_SMC_MEM_WIDTH_8 = 0, + PL353_SMC_MEM_WIDTH_16 = 1 +}; + +u32 pl353_smc_get_ecc_val(int ecc_reg); +bool pl353_smc_ecc_is_busy(void); +int pl353_smc_get_nand_int_status_raw(void); +void pl353_smc_clr_nand_int(void); +int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode); +int pl353_smc_set_ecc_pg_size(unsigned int pg_sz); +int pl353_smc_set_buswidth(unsigned int bw); +void pl353_smc_set_cycles(u32 timings[]); +#endif diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 06996ad4f2bc..1637385bcc17 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -67,6 +67,9 @@ extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); #else + +#include <linux/errno.h> + static inline int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) { diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h new file mode 100644 index 000000000000..54ade13a9b15 --- /dev/null +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * + */ + +#ifndef __MTK_CMDQ_H__ +#define __MTK_CMDQ_H__ + +#include <linux/mailbox_client.h> +#include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/timer.h> + +#define CMDQ_NO_TIMEOUT 0xffffffffu + +/** cmdq event maximum */ +#define CMDQ_MAX_EVENT 0x3ff + +struct cmdq_pkt; + +struct cmdq_client { + spinlock_t lock; + u32 pkt_cnt; + struct mbox_client client; + struct mbox_chan *chan; + struct timer_list timer; + u32 timeout_ms; /* in unit of microsecond */ +}; + +/** + * cmdq_mbox_create() - create CMDQ mailbox client and channel + * @dev: device of CMDQ mailbox client + * @index: index of CMDQ mailbox channel + * @timeout: timeout of a pkt execution by GCE, in unit of microsecond, set + * CMDQ_NO_TIMEOUT if a timer is not used. + * + * Return: CMDQ mailbox client pointer + */ +struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, + u32 timeout); + +/** + * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel + * @client: the CMDQ mailbox client + */ +void cmdq_mbox_destroy(struct cmdq_client *client); + +/** + * cmdq_pkt_create() - create a CMDQ packet + * @client: the CMDQ mailbox client + * @size: required CMDQ buffer size + * + * Return: CMDQ packet pointer + */ +struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size); + +/** + * cmdq_pkt_destroy() - destroy the CMDQ packet + * @pkt: the CMDQ packet + */ +void cmdq_pkt_destroy(struct cmdq_pkt *pkt); + +/** + * cmdq_pkt_write() - append write command to the CMDQ packet + * @pkt: the CMDQ packet + * @value: the specified target register value + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset); + +/** + * cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet + * @pkt: the CMDQ packet + * @value: the specified target register value + * @subsys: the CMDQ sub system code + * @offset: register offset from CMDQ sub system + * @mask: the specified target register mask + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value, + u32 subsys, u32 offset, u32 mask); + +/** + * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet + * @pkt: the CMDQ packet + * @event: the desired event type to "wait and CLEAR" + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event); + +/** + * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet + * @pkt: the CMDQ packet + * @event: the desired event to be cleared + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event); + +/** + * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ + * packet and call back at the end of done packet + * @pkt: the CMDQ packet + * @cb: called at the end of done packet + * @data: this data will pass back to cb + * + * Return: 0 for success; else the error code is returned + * + * Trigger CMDQ to asynchronously execute the CMDQ packet and call back + * at the end of done packet. Note that this is an ASYNC function. When the + * function returned, it may or may not be finished. + */ +int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, + void *data); + +/** + * cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet + * @pkt: the CMDQ packet + * + * Return: 0 for success; else the error code is returned + * + * Trigger CMDQ to execute the CMDQ packet. Note that this is a + * synchronous flush function. When the function returned, the recorded + * commands have been done. + */ +int cmdq_pkt_flush(struct cmdq_pkt *pkt); + +#endif /* __MTK_CMDQ_H__ */ diff --git a/include/linux/soc/qcom/qmi.h b/include/linux/soc/qcom/qmi.h index f4de33654a60..5efa2b67fa55 100644 --- a/include/linux/soc/qcom/qmi.h +++ b/include/linux/soc/qcom/qmi.h @@ -166,7 +166,7 @@ struct qmi_ops { struct qmi_txn { struct qmi_handle *qmi; - int id; + u16 id; struct mutex lock; struct completion completion; diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h index c4a5c9e9fb47..4be1aa4435ae 100644 --- a/include/soc/bcm2835/raspberrypi-firmware.h +++ b/include/soc/bcm2835/raspberrypi-firmware.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __SOC_RASPBERRY_FIRMWARE_H__ diff --git a/include/soc/qcom/cmd-db.h b/include/soc/qcom/cmd-db.h index 578180cbc134..af9722223925 100644 --- a/include/soc/qcom/cmd-db.h +++ b/include/soc/qcom/cmd-db.h @@ -18,9 +18,7 @@ enum cmd_db_hw_type { #if IS_ENABLED(CONFIG_QCOM_COMMAND_DB) u32 cmd_db_read_addr(const char *resource_id); -int cmd_db_read_aux_data(const char *resource_id, u8 *data, size_t len); - -size_t cmd_db_read_aux_data_len(const char *resource_id); +const void *cmd_db_read_aux_data(const char *resource_id, size_t *len); enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id); @@ -29,12 +27,8 @@ int cmd_db_ready(void); static inline u32 cmd_db_read_addr(const char *resource_id) { return 0; } -static inline int cmd_db_read_aux_data(const char *resource_id, u8 *data, - size_t len) -{ return -ENODEV; } - -static inline size_t cmd_db_read_aux_data_len(const char *resource_id) -{ return -ENODEV; } +static inline const void *cmd_db_read_aux_data(const char *resource_id, size_t *len) +{ return ERR_PTR(-ENODEV); } static inline enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id) { return -ENODEV; } diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h index 98d8d38b99a1..ab7f8796a260 100644 --- a/include/soc/tegra/bpmp-abi.h +++ b/include/soc/tegra/bpmp-abi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -40,7 +40,6 @@ * @file */ - /** * @defgroup MRQ MRQ Messages * @brief Messages sent to/from BPMP via IPC @@ -53,7 +52,7 @@ */ /** - * @addtogroup MRQ_Format Message Format + * @addtogroup MRQ_Format * @{ * The CPU requests the BPMP to perform a particular service by * sending it an IVC frame containing a single MRQ message. An MRQ @@ -76,7 +75,7 @@ /** * @ingroup MRQ_Format - * @brief header for an MRQ message + * @brief Header for an MRQ message * * Provides the MRQ number for the MRQ message: #mrq. The remainder of * the MRQ message is a payload (immediately following the @@ -86,7 +85,7 @@ struct mrq_request { /** @brief MRQ number of the request */ uint32_t mrq; /** - * @brief flags providing follow up directions to the receiver + * @brief Flags providing follow up directions to the receiver * * | Bit | Description | * |-----|--------------------------------------------| @@ -98,7 +97,7 @@ struct mrq_request { /** * @ingroup MRQ_Format - * @brief header for an MRQ response + * @brief Header for an MRQ response * * Provides an error code for the associated MRQ message. The * remainder of the MRQ response is a payload (immediately following @@ -106,9 +105,9 @@ struct mrq_request { * mrq_request::mrq */ struct mrq_response { - /** @brief error code for the MRQ request itself */ + /** @brief Error code for the MRQ request itself */ int32_t err; - /** @brief reserved for future use */ + /** @brief Reserved for future use */ uint32_t flags; } __ABI_PACKED; @@ -152,6 +151,14 @@ struct mrq_response { #define MRQ_TRACE_ITER 64 #define MRQ_RINGBUF_CONSOLE 65 #define MRQ_PG 66 +#define MRQ_CPU_NDIV_LIMITS 67 +#define MRQ_STRAP 68 +#define MRQ_UPHY 69 +#define MRQ_CPU_AUTO_CC3 70 +#define MRQ_QUERY_FW_TAG 71 +#define MRQ_FMON 72 +#define MRQ_EC 73 +#define MRQ_FBVOLT_STATUS 74 /** @} */ @@ -160,31 +167,35 @@ struct mrq_response { * @brief Maximum MRQ code to be sent by CPU software to * BPMP. Subject to change in future */ -#define MAX_CPU_MRQ_ID 66 +#define MAX_CPU_MRQ_ID 74 /** - * @addtogroup MRQ_Payloads Message Payloads + * @addtogroup MRQ_Payloads * @{ - * @defgroup Ping + * @defgroup Ping Ping * @defgroup Query_Tag Query Tag * @defgroup Module Loadable Modules - * @defgroup Trace - * @defgroup Debugfs - * @defgroup Reset - * @defgroup I2C - * @defgroup Clocks + * @defgroup Trace Trace + * @defgroup Debugfs Debug File System + * @defgroup Reset Reset + * @defgroup I2C I2C + * @defgroup Clocks Clocks * @defgroup ABI_info ABI Info - * @defgroup MC_Flush MC Flush - * @defgroup Powergating - * @defgroup Thermal + * @defgroup Powergating Power Gating + * @defgroup Thermal Thermal * @defgroup Vhint CPU Voltage hint - * @defgroup MRQ_Deprecated Deprecated MRQ messages - * @defgroup EMC - * @defgroup RingbufConsole + * @defgroup EMC EMC + * @defgroup CPU NDIV Limits + * @defgroup RingbufConsole Ring Buffer Console + * @defgroup Strap Straps + * @defgroup UPHY UPHY + * @defgroup CC3 Auto-CC3 + * @defgroup FMON FMON + * @defgroup EC EC + * @defgroup Fbvolt_status Fuse Burn Voltage Status * @} */ - /** * @ingroup MRQ_Codes * @def MRQ_PING @@ -214,20 +225,20 @@ struct mrq_response { /** * @ingroup Ping - * @brief request with #MRQ_PING + * @brief Request with #MRQ_PING * * Used by the sender of an #MRQ_PING message to request a pong from * recipient. The response from the recipient is computed based on * #challenge. */ struct mrq_ping_request { -/** @brief arbitrarily chosen value */ +/** @brief Arbitrarily chosen value */ uint32_t challenge; } __ABI_PACKED; /** * @ingroup Ping - * @brief response to #MRQ_PING + * @brief Response to #MRQ_PING * * Sent in response to an #MRQ_PING message. #reply should be the * mrq_ping_request challenge left shifted by 1 with the carry-bit @@ -235,14 +246,16 @@ struct mrq_ping_request { * */ struct mrq_ping_response { - /** @brief response to the MRQ_PING challege */ + /** @brief Response to the MRQ_PING challege */ uint32_t reply; } __ABI_PACKED; /** * @ingroup MRQ_Codes * @def MRQ_QUERY_TAG - * @brief Query BPMP firmware's tag (i.e. version information) + * @brief Query BPMP firmware's tag (i.e. unique identifer) + * + * @deprecated Use #MRQ_QUERY_FW_TAG instead. * * * Platforms: All * * Initiators: CCPLEX @@ -254,25 +267,50 @@ struct mrq_ping_response { /** * @ingroup Query_Tag - * @brief request with #MRQ_QUERY_TAG - * - * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory - * pointed by #addr with BPMP firmware header. + * @brief Request with #MRQ_QUERY_TAG * - * The sender is reponsible for ensuring that #addr is mapped in to - * the recipient's address map. + * @deprecated This structure will be removed in future version. + * Use MRQ_QUERY_FW_TAG instead. */ struct mrq_query_tag_request { - /** @brief base address to store the firmware header */ + /** @brief Base address to store the firmware tag */ uint32_t addr; } __ABI_PACKED; + /** * @ingroup MRQ_Codes - * @def MRQ_MODULE_LOAD - * @brief dynamically load a BPMP code module + * @def MRQ_QUERY_FW_TAG + * @brief Query BPMP firmware's tag (i.e. unique identifier) * * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_query_fw_tag_response + * + */ + +/** + * @ingroup Query_Tag + * @brief Response to #MRQ_QUERY_FW_TAG + * + * Sent in response to #MRQ_QUERY_FW_TAG message. #tag contains the unique + * identifier for the version of firmware issuing the reply. + * + */ +struct mrq_query_fw_tag_response { + /** @brief Array to store tag information */ + uint8_t tag[32]; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_LOAD + * @brief Dynamically load a BPMP code module + * + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_module_load_request @@ -284,7 +322,7 @@ struct mrq_query_tag_request { /** * @ingroup Module - * @brief request with #MRQ_MODULE_LOAD + * @brief Request with #MRQ_MODULE_LOAD * * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically * load the code located at #phys_addr and having size #size @@ -300,29 +338,31 @@ struct mrq_query_tag_request { * */ struct mrq_module_load_request { - /** @brief base address of the code to load. Treated as (void *) */ + /** @brief Base address of the code to load. Treated as (void *) */ uint32_t phys_addr; /* (void *) */ - /** @brief size in bytes of code to load */ + /** @brief Size in bytes of code to load */ uint32_t size; } __ABI_PACKED; /** * @ingroup Module - * @brief response to #MRQ_MODULE_LOAD + * @brief Response to #MRQ_MODULE_LOAD * * @todo document mrq_response::err */ struct mrq_module_load_response { - /** @brief handle to the loaded module */ + /** @brief Handle to the loaded module */ uint32_t base; } __ABI_PACKED; +/** @endcond*/ /** * @ingroup MRQ_Codes * @def MRQ_MODULE_UNLOAD - * @brief unload a previously loaded code module + * @brief Unload a previously loaded code module * - * * Platforms: All + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_module_unload_request @@ -333,20 +373,21 @@ struct mrq_module_load_response { /** * @ingroup Module - * @brief request with #MRQ_MODULE_UNLOAD + * @brief Request with #MRQ_MODULE_UNLOAD * * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded * module be unloaded. */ struct mrq_module_unload_request { - /** @brief handle of the module to unload */ + /** @brief Handle of the module to unload */ uint32_t base; } __ABI_PACKED; +/** @endcond*/ /** * @ingroup MRQ_Codes * @def MRQ_TRACE_MODIFY - * @brief modify the set of enabled trace events + * @brief Modify the set of enabled trace events * * * Platforms: All * * Initiators: CCPLEX @@ -359,22 +400,22 @@ struct mrq_module_unload_request { /** * @ingroup Trace - * @brief request with #MRQ_TRACE_MODIFY + * @brief Request with #MRQ_TRACE_MODIFY * * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace * events. #set takes precedence for any bit set in both #set and * #clr. */ struct mrq_trace_modify_request { - /** @brief bit mask of trace events to disable */ + /** @brief Bit mask of trace events to disable */ uint32_t clr; - /** @brief bit mask of trace events to enable */ + /** @brief Bit mask of trace events to enable */ uint32_t set; } __ABI_PACKED; /** * @ingroup Trace - * @brief response to #MRQ_TRACE_MODIFY + * @brief Response to #MRQ_TRACE_MODIFY * * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the * state of which events are enabled after the recipient acted on the @@ -382,7 +423,7 @@ struct mrq_trace_modify_request { * */ struct mrq_trace_modify_response { - /** @brief bit mask of trace event enable states */ + /** @brief Bit mask of trace event enable states */ uint32_t mask; } __ABI_PACKED; @@ -407,7 +448,7 @@ struct mrq_trace_modify_response { /** * @ingroup Trace - * @brief request with #MRQ_WRITE_TRACE + * @brief Request with #MRQ_WRITE_TRACE * * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace * data from the recipient's local buffer to the output buffer. #area @@ -420,22 +461,22 @@ struct mrq_trace_modify_response { * overwrites. */ struct mrq_write_trace_request { - /** @brief base address of output buffer */ + /** @brief Base address of output buffer */ uint32_t area; - /** @brief size in bytes of the output buffer */ + /** @brief Size in bytes of the output buffer */ uint32_t size; } __ABI_PACKED; /** * @ingroup Trace - * @brief response to #MRQ_WRITE_TRACE + * @brief Response to #MRQ_WRITE_TRACE * * Once this response is sent, the respondent will not access the * output buffer further. */ struct mrq_write_trace_response { /** - * @brief flag whether more data remains in local buffer + * @brief Flag whether more data remains in local buffer * * Value is 1 if the entire local trace buffer has been * drained to the outputbuffer. Value is 0 otherwise. @@ -456,9 +497,10 @@ struct mrq_threaded_ping_response { /** * @ingroup MRQ_Codes * @def MRQ_MODULE_MAIL - * @brief send a message to a loadable module + * @brief Send a message to a loadable module * - * * Platforms: All + * * Platforms: T210, T214, T186 + * @cond (bpmp_t210 || bpmp_t214 || bpmp_t186) * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_module_mail_request @@ -469,12 +511,12 @@ struct mrq_threaded_ping_response { /** * @ingroup Module - * @brief request with #MRQ_MODULE_MAIL + * @brief Request with #MRQ_MODULE_MAIL */ struct mrq_module_mail_request { - /** @brief handle to the previously loaded module */ + /** @brief Handle to the previously loaded module */ uint32_t base; - /** @brief module-specific mail payload + /** @brief Module-specific mail payload * * The length of data[ ] is unknown to the BPMP core firmware * but it is limited to the size of an IPC message. @@ -484,23 +526,24 @@ struct mrq_module_mail_request { /** * @ingroup Module - * @brief response to #MRQ_MODULE_MAIL + * @brief Response to #MRQ_MODULE_MAIL */ struct mrq_module_mail_response { - /** @brief module-specific mail payload + /** @brief Module-specific mail payload * * The length of data[ ] is unknown to the BPMP core firmware * but it is limited to the size of an IPC message. */ uint8_t data[EMPTY_ARRAY]; } __ABI_PACKED; +/** @endcond */ /** * @ingroup MRQ_Codes * @def MRQ_DEBUGFS * @brief Interact with BPMP's debugfs file nodes * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_debugfs_request @@ -529,65 +572,70 @@ struct mrq_module_mail_response { * * @} */ + /** @ingroup Debugfs */ enum mrq_debugfs_commands { + /** @brief Perform read */ CMD_DEBUGFS_READ = 1, + /** @brief Perform write */ CMD_DEBUGFS_WRITE = 2, + /** @brief Perform dumping directory */ CMD_DEBUGFS_DUMPDIR = 3, + /** @brief Not a command */ CMD_DEBUGFS_MAX }; /** * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command + * @brief Parameters for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_fileop_request { - /** @brief physical address pointing at filename */ + /** @brief Physical address pointing at filename */ uint32_t fnameaddr; - /** @brief length in bytes of filename buffer */ + /** @brief Length in bytes of filename buffer */ uint32_t fnamelen; - /** @brief physical address pointing to data buffer */ + /** @brief Physical address pointing to data buffer */ uint32_t dataaddr; - /** @brief length in bytes of data buffer */ + /** @brief Length in bytes of data buffer */ uint32_t datalen; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief parameters for CMD_DEBUGFS_READ/WRITE command + * @brief Parameters for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_dumpdir_request { - /** @brief physical address pointing to data buffer */ + /** @brief Physical address pointing to data buffer */ uint32_t dataaddr; - /** @brief length in bytes of data buffer */ + /** @brief Length in bytes of data buffer */ uint32_t datalen; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_READ/WRITE command + * @brief Response data for CMD_DEBUGFS_READ/WRITE command */ struct cmd_debugfs_fileop_response { - /** @brief always 0 */ + /** @brief Always 0 */ uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ + /** @brief Number of bytes read from or written to data buffer */ uint32_t nbytes; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief response data for CMD_DEBUGFS_DUMPDIR command + * @brief Response data for CMD_DEBUGFS_DUMPDIR command */ struct cmd_debugfs_dumpdir_response { - /** @brief always 0 */ + /** @brief Always 0 */ uint32_t reserved; - /** @brief number of bytes read from or written to data buffer */ + /** @brief Number of bytes read from or written to data buffer */ uint32_t nbytes; } __ABI_PACKED; /** * @ingroup Debugfs - * @brief request with #MRQ_DEBUGFS. + * @brief Request with #MRQ_DEBUGFS. * * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs * command to execute. Legal commands are the values of @ref @@ -601,6 +649,7 @@ struct cmd_debugfs_dumpdir_response { * |CMD_DEBUGFS_DUMPDIR|dumpdir| */ struct mrq_debugfs_request { + /** @brief Sub-command (@ref mrq_debugfs_commands) */ uint32_t cmd; union { struct cmd_debugfs_fileop_request fop; @@ -612,14 +661,14 @@ struct mrq_debugfs_request { * @ingroup Debugfs */ struct mrq_debugfs_response { - /** @brief always 0 */ + /** @brief Always 0 */ int32_t reserved; union { - /** @brief response data for CMD_DEBUGFS_READ OR + /** @brief Response data for CMD_DEBUGFS_READ OR * CMD_DEBUGFS_WRITE command */ struct cmd_debugfs_fileop_response fop; - /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ + /** @brief Response data for CMD_DEBUGFS_DUMPDIR command */ struct cmd_debugfs_dumpdir_response dumpdir; } __UNION_ANON; } __ABI_PACKED; @@ -633,57 +682,58 @@ struct mrq_debugfs_response { #define DEBUGFS_S_IWUSR (1 << 7) /** @} */ - /** * @ingroup MRQ_Codes * @def MRQ_RESET - * @brief reset an IP block + * @brief Reset an IP block * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_reset_request * * Response Payload: @ref mrq_reset_response + * + * @addtogroup Reset + * @{ */ -/** - * @ingroup Reset - */ enum mrq_reset_commands { + /** @brief Assert module reset */ CMD_RESET_ASSERT = 1, + /** @brief Deassert module reset */ CMD_RESET_DEASSERT = 2, + /** @brief Assert and deassert the module reset */ CMD_RESET_MODULE = 3, + /** @brief Get the highest reset ID */ CMD_RESET_GET_MAX_ID = 4, - CMD_RESET_MAX, /* not part of ABI and subject to change */ + /** @brief Not part of ABI and subject to change */ + CMD_RESET_MAX, }; /** - * @ingroup Reset - * @brief request with MRQ_RESET + * @brief Request with MRQ_RESET * * Used by the sender of an #MRQ_RESET message to request BPMP to * assert or or deassert a given reset line. */ struct mrq_reset_request { - /** @brief reset action to perform (@enum mrq_reset_commands) */ + /** @brief Reset action to perform (@ref mrq_reset_commands) */ uint32_t cmd; - /** @brief id of the reset to affected */ + /** @brief Id of the reset to affected */ uint32_t reset_id; } __ABI_PACKED; /** - * @ingroup Reset * @brief Response for MRQ_RESET sub-command CMD_RESET_GET_MAX_ID. When * this sub-command is not supported, firmware will return -BPMP_EBADCMD * in mrq_response::err. */ struct cmd_reset_get_max_id_response { - /** @brief max reset id */ + /** @brief Max reset id */ uint32_t max_id; } __ABI_PACKED; /** - * @ingroup Reset * @brief Response with MRQ_RESET * * Each sub-command supported by @ref mrq_reset_request may return @@ -703,32 +753,25 @@ struct mrq_reset_response { } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_I2C - * @brief issue an i2c transaction + * @brief Issue an i2c transaction * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_i2c_request * * Response Payload: @ref mrq_i2c_response - */ - -/** + * * @addtogroup I2C * @{ */ #define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) #define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) -/** @} */ -/** - * @ingroup I2C - * @name Serial I2C flags - * Use these flags with serial_i2c_request::flags - * @{ - */ #define SERIALI2C_TEN 0x0010 #define SERIALI2C_RD 0x0001 #define SERIALI2C_STOP 0x8000 @@ -737,15 +780,13 @@ struct mrq_reset_response { #define SERIALI2C_IGNORE_NAK 0x1000 #define SERIALI2C_NO_RD_ACK 0x0800 #define SERIALI2C_RECV_LEN 0x0400 -/** @} */ -/** @ingroup I2C */ + enum { CMD_I2C_XFER = 1 }; /** - * @ingroup I2C - * @brief serializable i2c request + * @brief Serializable i2c request * * Instances of this structure are packed (little-endian) into * cmd_i2c_xfer_request::data_buf. Each instance represents a single @@ -762,80 +803,75 @@ enum { struct serial_i2c_request { /** @brief I2C slave address */ uint16_t addr; - /** @brief bitmask of SERIALI2C_ flags */ + /** @brief Bitmask of SERIALI2C_ flags */ uint16_t flags; - /** @brief length of I2C transaction in bytes */ + /** @brief Length of I2C transaction in bytes */ uint16_t len; - /** @brief for write transactions only, #len bytes of data */ + /** @brief For write transactions only, #len bytes of data */ uint8_t data[]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief trigger one or more i2c transactions + * @brief Trigger one or more i2c transactions */ struct cmd_i2c_xfer_request { - /** @brief valid bus number from mach-t186/i2c-t186.h*/ + /** @brief Valid bus number from @ref bpmp_i2c_ids*/ uint32_t bus_id; - /** @brief count of valid bytes in #data_buf*/ + /** @brief Count of valid bytes in #data_buf*/ uint32_t data_size; - /** @brief serialized packed instances of @ref serial_i2c_request*/ + /** @brief Serialized packed instances of @ref serial_i2c_request*/ uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief container for data read from the i2c bus + * @brief Container for data read from the i2c bus * * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute * zero or more I2C reads. The data read from the bus is serialized * into #data_buf. */ struct cmd_i2c_xfer_response { - /** @brief count of valid bytes in #data_buf*/ + /** @brief Count of valid bytes in #data_buf*/ uint32_t data_size; - /** @brief i2c read data */ + /** @brief I2c read data */ uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; } __ABI_PACKED; /** - * @ingroup I2C - * @brief request with #MRQ_I2C + * @brief Request with #MRQ_I2C */ struct mrq_i2c_request { - /** @brief always CMD_I2C_XFER (i.e. 1) */ + /** @brief Always CMD_I2C_XFER (i.e. 1) */ uint32_t cmd; - /** @brief parameters of the transfer request */ + /** @brief Parameters of the transfer request */ struct cmd_i2c_xfer_request xfer; } __ABI_PACKED; /** - * @ingroup I2C - * @brief response to #MRQ_I2C + * @brief Response to #MRQ_I2C */ struct mrq_i2c_response { struct cmd_i2c_xfer_response xfer; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_CLK + * @brief Perform a clock operation * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_clk_request * * Response Payload: @ref mrq_clk_response + * * @addtogroup Clocks * @{ */ - -/** - * @name MRQ_CLK sub-commands - * @{ - */ enum { CMD_CLK_GET_RATE = 1, CMD_CLK_SET_RATE = 2, @@ -847,20 +883,13 @@ enum { CMD_CLK_DISABLE = 8, CMD_CLK_GET_ALL_INFO = 14, CMD_CLK_GET_MAX_CLK_ID = 15, + CMD_CLK_GET_FMAX_AT_VMIN = 16, CMD_CLK_MAX, }; -/** @} */ -/** - * @name MRQ_CLK properties - * Flag bits for cmd_clk_properties_response::flags and - * cmd_clk_get_all_info_response::flags - * @{ - */ #define BPMP_CLK_HAS_MUX (1 << 0) #define BPMP_CLK_HAS_SET_RATE (1 << 1) #define BPMP_CLK_IS_ROOT (1 << 2) -/** @} */ #define MRQ_CLK_NAME_MAXLEN 40 #define MRQ_CLK_MAX_PARENTS 16 @@ -959,11 +988,19 @@ struct cmd_clk_get_max_clk_id_request { struct cmd_clk_get_max_clk_id_response { uint32_t max_id; } __ABI_PACKED; -/** @} */ + +/** @private */ +struct cmd_clk_get_fmax_at_vmin_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_fmax_at_vmin_response { + int64_t rate; +} __ABI_PACKED; /** * @ingroup Clocks - * @brief request with #MRQ_CLK + * @brief Request with #MRQ_CLK * * Used by the sender of an #MRQ_CLK message to control clocks. The * clk_request is split into several sub-commands. Some sub-commands @@ -982,11 +1019,13 @@ struct cmd_clk_get_max_clk_id_response { * |CMD_CLK_DISABLE |- | * |CMD_CLK_GET_ALL_INFO |- | * |CMD_CLK_GET_MAX_CLK_ID |- | + * |CMD_CLK_GET_FMAX_AT_VMIN |- + * | * */ struct mrq_clk_request { - /** @brief sub-command and clock id concatenated to 32-bit word. + /** @brief Sub-command and clock id concatenated to 32-bit word. * - bits[31..24] is the sub-cmd. * - bits[23..0] is the clock id */ @@ -1010,12 +1049,14 @@ struct mrq_clk_request { struct cmd_clk_get_all_info_request clk_get_all_info; /** @private */ struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; + /** @private */ + struct cmd_clk_get_fmax_at_vmin_request clk_get_fmax_at_vmin; } __UNION_ANON; } __ABI_PACKED; /** * @ingroup Clocks - * @brief response to MRQ_CLK + * @brief Response to MRQ_CLK * * Each sub-command supported by @ref mrq_clk_request may return * sub-command-specific data. Some do and some do not as indicated in @@ -1033,6 +1074,7 @@ struct mrq_clk_request { * |CMD_CLK_DISABLE |- | * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | + * |CMD_CLK_GET_FMAX_AT_VMIN |clk_get_fmax_at_vmin | * */ @@ -1050,13 +1092,16 @@ struct mrq_clk_response { struct cmd_clk_is_enabled_response clk_is_enabled; struct cmd_clk_get_all_info_response clk_get_all_info; struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; + struct cmd_clk_get_fmax_at_vmin_response clk_get_fmax_at_vmin; } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_QUERY_ABI - * @brief check if an MRQ is implemented + * @brief Check if an MRQ is implemented * * * Platforms: All * * Initiators: Any @@ -1067,7 +1112,7 @@ struct mrq_clk_response { /** * @ingroup ABI_info - * @brief request with MRQ_QUERY_ABI + * @brief Request with MRQ_QUERY_ABI * * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported * by the recipient. @@ -1079,7 +1124,7 @@ struct mrq_query_abi_request { /** * @ingroup ABI_info - * @brief response to MRQ_QUERY_ABI + * @brief Response to MRQ_QUERY_ABI * * @note mrq_response::err of 0 indicates that the query was * successful, not that the MRQ itself is supported! @@ -1092,19 +1137,19 @@ struct mrq_query_abi_response { /** * @ingroup MRQ_Codes * @def MRQ_PG_READ_STATE - * @brief read the power-gating state of a partition + * @brief Read the power-gating state of a partition * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_read_state_request * * Response Payload: @ref mrq_pg_read_state_response - * @addtogroup Powergating - * @{ */ /** - * @brief request with #MRQ_PG_READ_STATE + * @ingroup Powergating + * @brief Request with #MRQ_PG_READ_STATE * * Used by MRQ_PG_READ_STATE call to read the current state of a * partition. @@ -1115,39 +1160,40 @@ struct mrq_pg_read_state_request { } __ABI_PACKED; /** - * @brief response to MRQ_PG_READ_STATE + * @ingroup Powergating + * @brief Response to MRQ_PG_READ_STATE * @todo define possible errors. */ struct mrq_pg_read_state_response { - /** @brief read as don't care */ + /** @brief Read as don't care */ uint32_t sram_state; - /** @brief state of power partition + /** @brief State of power partition * * 0 : off * * 1 : on */ uint32_t logic_state; } __ABI_PACKED; - +/** @endcond*/ /** @} */ /** * @ingroup MRQ_Codes * @def MRQ_PG_UPDATE_STATE - * @brief modify the power-gating state of a partition. In contrast to + * @brief Modify the power-gating state of a partition. In contrast to * MRQ_PG calls, the operations that change state (on/off) of power * partition are reference counted. * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_update_state_request * * Response Payload: N/A - * @addtogroup Powergating - * @{ */ /** - * @brief request with mrq_pg_update_state_request + * @ingroup Powergating + * @brief Request with mrq_pg_update_state_request * * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the * state of a power partition #partition_id. @@ -1155,20 +1201,20 @@ struct mrq_pg_read_state_response { struct mrq_pg_update_state_request { /** @brief ID of partition */ uint32_t partition_id; - /** @brief secondary control of power partition + /** @brief Secondary control of power partition * @details Ignored by many versions of the BPMP * firmware. For maximum compatibility, set the value - * according to @logic_state + * according to @ref logic_state * * 0x1: power ON partition (@ref logic_state == 0x3) * * 0x3: power OFF partition (@ref logic_state == 0x1) */ uint32_t sram_state; - /** @brief controls state of power partition, legal values are + /** @brief Controls state of power partition, legal values are * * 0x1 : power OFF partition * * 0x3 : power ON partition */ uint32_t logic_state; - /** @brief change state of clocks of the power partition, legal values + /** @brief Change state of clocks of the power partition, legal values * * 0x0 : do not change clock state * * 0x1 : disable partition clocks (only applicable when * @ref logic_state == 0x1) @@ -1177,7 +1223,7 @@ struct mrq_pg_update_state_request { */ uint32_t clock_state; } __ABI_PACKED; -/** @} */ +/** @endcond*/ /** * @ingroup MRQ_Codes @@ -1186,19 +1232,20 @@ struct mrq_pg_update_state_request { * MRQ_PG_UPDATE_STATE, operations that change the power partition * state are NOT reference counted * - * * Platforms: T186 + * @note BPMP-FW forcefully turns off some partitions as part of SC7 entry + * because their state cannot be adequately restored on exit. Therefore, + * it is recommended to power off all domains via MRQ_PG prior to SC7 entry. + * See @ref bpmp_pdomain_ids for further detail. + * + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_pg_request * * Response Payload: @ref mrq_pg_response + * * @addtogroup Powergating * @{ */ - -/** - * @name MRQ_PG sub-commands - * @{ - */ enum mrq_pg_cmd { /** * @brief Check whether the BPMP driver supports the specified @@ -1232,7 +1279,7 @@ enum mrq_pg_cmd { CMD_PG_GET_STATE = 2, /** - * @brief get the name string of specified power domain id. + * @brief Get the name string of specified power domain id. * * mrq_response:err is * 0: Success @@ -1242,7 +1289,7 @@ enum mrq_pg_cmd { /** - * @brief get the highest power domain id in the system. Not + * @brief Get the highest power domain id in the system. Not * all IDs between 0 and max_id are valid IDs. * * mrq_response:err is @@ -1251,35 +1298,36 @@ enum mrq_pg_cmd { */ CMD_PG_GET_MAX_ID = 4, }; -/** @} */ #define MRQ_PG_NAME_MAXLEN 40 -/** - * @brief possible power domain states in - * cmd_pg_set_state_request:state and cmd_pg_get_state_response:state. - * PG_STATE_OFF: power domain is OFF - * PG_STATE_ON: power domain is ON - * PG_STATE_RUNNING: power domain is ON and made into directly usable - * state by turning on the clocks associated with - * the domain - */ enum pg_states { + /** @brief Power domain is OFF */ PG_STATE_OFF = 0, + /** @brief Power domain is ON */ PG_STATE_ON = 1, + /** + * @brief a legacy state where power domain and the clock + * associated to the domain are ON. + * This state is only supported in T186, and the use of it is + * deprecated. + */ PG_STATE_RUNNING = 2, }; struct cmd_pg_query_abi_request { - uint32_t type; /* enum mrq_pg_cmd */ + /** @ref mrq_pg_cmd */ + uint32_t type; } __ABI_PACKED; struct cmd_pg_set_state_request { - uint32_t state; /* enum pg_states */ + /** @ref pg_states */ + uint32_t state; } __ABI_PACKED; struct cmd_pg_get_state_response { - uint32_t state; /* enum pg_states */ + /** @ref pg_states */ + uint32_t state; } __ABI_PACKED; struct cmd_pg_get_name_response { @@ -1291,8 +1339,7 @@ struct cmd_pg_get_max_id_response { } __ABI_PACKED; /** - * @ingroup Powergating - * @brief request with #MRQ_PG + * @brief Request with #MRQ_PG * * Used by the sender of an #MRQ_PG message to control power * partitions. The pg_request is split into several sub-commands. Some @@ -1308,7 +1355,6 @@ struct cmd_pg_get_max_id_response { * |CMD_PG_GET_MAX_ID | - | * */ - struct mrq_pg_request { uint32_t cmd; uint32_t id; @@ -1319,8 +1365,7 @@ struct mrq_pg_request { } __ABI_PACKED; /** - * @ingroup Powergating - * @brief response to MRQ_PG + * @brief Response to MRQ_PG * * Each sub-command supported by @ref mrq_pg_request may return * sub-command-specific data. Some do and some do not as indicated in @@ -1333,9 +1378,7 @@ struct mrq_pg_request { * |CMD_PG_GET_STATE | get_state | * |CMD_PG_GET_NAME | get_name | * |CMD_PG_GET_MAX_ID | get_max_id | - * */ - struct mrq_pg_response { union { struct cmd_pg_get_state_response get_state; @@ -1344,12 +1387,14 @@ struct mrq_pg_response { } __UNION_ANON; } __ABI_PACKED; +/** @} */ + /** * @ingroup MRQ_Codes * @def MRQ_THERMAL - * @brief interact with BPMP thermal framework + * @brief Interact with BPMP thermal framework * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: Any * * Request Payload: TODO @@ -1562,17 +1607,18 @@ union mrq_thermal_bpmp_to_host_response { * @brief Query CPU voltage hint data * * * Platforms: T186 + * @cond bpmp_t186 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: @ref mrq_cpu_vhint_request * * Response Payload: N/A * - * @addtogroup Vhint CPU Voltage hint + * @addtogroup Vhint * @{ */ /** - * @brief request with #MRQ_CPU_VHINT + * @brief Request with #MRQ_CPU_VHINT * * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data * from BPMP to memory space pointed by #addr. CCPLEX is responsible @@ -1581,16 +1627,16 @@ union mrq_thermal_bpmp_to_host_response { */ struct mrq_cpu_vhint_request { /** @brief IOVA address for the #cpu_vhint_data */ - uint32_t addr; /* struct cpu_vhint_data * */ + uint32_t addr; /** @brief ID of the cluster whose data is requested */ - uint32_t cluster_id; /* enum cluster_id */ + uint32_t cluster_id; } __ABI_PACKED; /** - * @brief description of the CPU v/f relation + * @brief Description of the CPU v/f relation * - * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of - * struct mrq_cpu_vhint_request + * Used by #MRQ_CPU_VHINT call to carry data pointed by + * #mrq_cpu_vhint_request::addr */ struct cpu_vhint_data { uint32_t ref_clk_hz; /**< reference frequency in Hz */ @@ -1612,7 +1658,7 @@ struct cpu_vhint_data { /** reserved for future use */ uint16_t reserved[328]; } __ABI_PACKED; - +/** @endcond */ /** @} */ /** @@ -1620,7 +1666,7 @@ struct cpu_vhint_data { * @def MRQ_ABI_RATCHET * @brief ABI ratchet value query * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: Any * * Targets: BPMP * * Request Payload: @ref mrq_abi_ratchet_request @@ -1630,7 +1676,7 @@ struct cpu_vhint_data { */ /** - * @brief an ABI compatibility mechanism + * @brief An ABI compatibility mechanism * * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future * revision of this header file. @@ -1644,7 +1690,7 @@ struct cpu_vhint_data { #define BPMP_ABI_RATCHET_VALUE 3 /** - * @brief request with #MRQ_ABI_RATCHET. + * @brief Request with #MRQ_ABI_RATCHET. * * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header * against which the requester was compiled. @@ -1657,12 +1703,12 @@ struct cpu_vhint_data { * Otherwise, err shall be 0. */ struct mrq_abi_ratchet_request { - /** @brief requester's ratchet value */ + /** @brief Requester's ratchet value */ uint16_t ratchet; }; /** - * @brief response to #MRQ_ABI_RATCHET + * @brief Response to #MRQ_ABI_RATCHET * * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header * against which BPMP firwmare was compiled. @@ -1685,9 +1731,9 @@ struct mrq_abi_ratchet_response { /** * @ingroup MRQ_Codes * @def MRQ_EMC_DVFS_LATENCY - * @brief query frequency dependent EMC DVFS latency + * @brief Query frequency dependent EMC DVFS latency * - * * Platforms: T186 + * * Platforms: T186, T194 * * Initiators: CCPLEX * * Targets: BPMP * * Request Payload: N/A @@ -1697,7 +1743,7 @@ struct mrq_abi_ratchet_response { */ /** - * @brief used by @ref mrq_emc_dvfs_latency_response + * @brief Used by @ref mrq_emc_dvfs_latency_response */ struct emc_dvfs_latency { /** @brief EMC frequency in kHz */ @@ -1708,10 +1754,10 @@ struct emc_dvfs_latency { #define EMC_DVFS_LATENCY_MAX_SIZE 14 /** - * @brief response to #MRQ_EMC_DVFS_LATENCY + * @brief Response to #MRQ_EMC_DVFS_LATENCY */ struct mrq_emc_dvfs_latency_response { - /** @brief the number valid entries in #pairs */ + /** @brief The number valid entries in #pairs */ uint32_t num_pairs; /** @brief EMC <frequency, latency> information */ struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; @@ -1721,8 +1767,96 @@ struct mrq_emc_dvfs_latency_response { /** * @ingroup MRQ_Codes + * @def MRQ_CPU_NDIV_LIMITS + * @brief CPU freq. limits in ndiv + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_ndiv_limits_request + * * Response Payload: @ref mrq_cpu_ndiv_limits_response + * @addtogroup CPU + * @{ + */ + +/** + * @brief Request for ndiv limits of a cluster + */ +struct mrq_cpu_ndiv_limits_request { + /** @brief Enum cluster_id */ + uint32_t cluster_id; +} __ABI_PACKED; + +/** + * @brief Response to #MRQ_CPU_NDIV_LIMITS + */ +struct mrq_cpu_ndiv_limits_response { + /** @brief Reference frequency in Hz */ + uint32_t ref_clk_hz; + /** @brief Post divider value */ + uint16_t pdiv; + /** @brief Input divider value */ + uint16_t mdiv; + /** @brief FMAX expressed with max NDIV value */ + uint16_t ndiv_max; + /** @brief Minimum allowed NDIV value */ + uint16_t ndiv_min; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_AUTO_CC3 + * @brief Query CPU cluster auto-CC3 configuration + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_auto_cc3_request + * * Response Payload: @ref mrq_cpu_auto_cc3_response + * @addtogroup CC3 + * + * Queries from BPMP auto-CC3 configuration (allowed/not allowed) for a + * specified cluster. CCPLEX s/w uses this information to override its own + * device tree auto-CC3 settings, so that BPMP device tree is a single source of + * auto-CC3 platform configuration. + * + * @{ + */ + +/** + * @brief Request for auto-CC3 configuration of a cluster + */ +struct mrq_cpu_auto_cc3_request { + /** @brief Enum cluster_id (logical cluster id, known to CCPLEX s/w) */ + uint32_t cluster_id; +} __ABI_PACKED; + +/** + * @brief Response to #MRQ_CPU_AUTO_CC3 + */ +struct mrq_cpu_auto_cc3_response { + /** + * @brief auto-CC3 configuration + * + * - bits[31..10] reserved. + * - bits[9..1] cc3 ndiv + * - bit [0] if "1" auto-CC3 is allowed, if "0" auto-CC3 is not allowed + */ + uint32_t auto_cc3_config; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes * @def MRQ_TRACE_ITER - * @brief manage the trace iterator + * @brief Manage the trace iterator * * * Platforms: All * * Initiators: CCPLEX @@ -1735,12 +1869,12 @@ struct mrq_emc_dvfs_latency_response { enum { /** @brief (re)start the tracing now. Ignore older events */ TRACE_ITER_INIT = 0, - /** @brief clobber all events in the trace buffer */ + /** @brief Clobber all events in the trace buffer */ TRACE_ITER_CLEAN = 1 }; /** - * @brief request with #MRQ_TRACE_ITER + * @brief Request with #MRQ_TRACE_ITER */ struct mrq_trace_iter_request { /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ @@ -1900,7 +2034,7 @@ struct cmd_ringbuf_console_get_fifo_resp { */ struct mrq_ringbuf_console_host_to_bpmp_request { /** - * @brief type of request. Values listed in enum + * @brief Type of request. Values listed in enum * #mrq_ringbuf_console_host_to_bpmp_cmd. */ uint32_t type; @@ -1927,49 +2061,616 @@ union mrq_ringbuf_console_bpmp_to_host_response { } __ABI_PACKED; /** @} */ -/* - * 4. Enumerations +/** + * @ingroup MRQ_Codes + * @def MRQ_STRAP + * @brief Set a strap value controlled by BPMP + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_strap_request + * * Response Payload: N/A + * @addtogroup Strap + * + * A strap is an input that is sampled by a hardware unit during the + * unit's startup process. The sampled value of a strap affects the + * behavior of the unit until the unit is restarted. Many hardware + * units sample their straps at the instant that their resets are + * deasserted. + * + * BPMP owns registers which act as straps to various units. It + * exposes limited control of those straps via #MRQ_STRAP. + * + * @{ */ +enum mrq_strap_cmd { + /** @private */ + STRAP_RESERVED = 0, + /** @brief Set a strap value */ + STRAP_SET = 1 +}; -/* - * 4.1 CPU enumerations +/** + * @brief Request with #MRQ_STRAP + */ +struct mrq_strap_request { + /** @brief @ref mrq_strap_cmd */ + uint32_t cmd; + /** @brief Strap ID from @ref Strap_Ids */ + uint32_t id; + /** @brief Desired value for strap (if cmd is #STRAP_SET) */ + uint32_t value; +} __ABI_PACKED; + +/** + * @defgroup Strap_Ids Strap Identifiers + * @} + */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_UPHY + * @brief Perform a UPHY operation * - * See <mach-t186/system-t186.h> + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_uphy_request + * * Response Payload: @ref mrq_uphy_response * - * 4.2 CPU Cluster enumerations + * @addtogroup UPHY + * @{ + */ +enum { + CMD_UPHY_PCIE_LANE_MARGIN_CONTROL = 1, + CMD_UPHY_PCIE_LANE_MARGIN_STATUS = 2, + CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT = 3, + CMD_UPHY_PCIE_CONTROLLER_STATE = 4, + CMD_UPHY_MAX, +}; + +struct cmd_uphy_margin_control_request { + /** @brief Enable margin */ + int32_t en; + /** @brief Clear the number of error and sections */ + int32_t clr; + /** @brief Set x offset (1's complement) for left/right margin type (y should be 0) */ + uint32_t x; + /** @brief Set y offset (1's complement) for left/right margin type (x should be 0) */ + uint32_t y; + /** @brief Set number of bit blocks for each margin section */ + uint32_t nblks; +} __ABI_PACKED; + +struct cmd_uphy_margin_status_response { + /** @brief Number of errors observed */ + uint32_t status; +} __ABI_PACKED; + +struct cmd_uphy_ep_controller_pll_init_request { + /** @brief EP controller number, valid: 0, 4, 5 */ + uint8_t ep_controller; +} __ABI_PACKED; + +struct cmd_uphy_pcie_controller_state_request { + /** @brief PCIE controller number, valid: 0, 1, 2, 3, 4 */ + uint8_t pcie_controller; + uint8_t enable; +} __ABI_PACKED; + +/** + * @ingroup UPHY + * @brief Request with #MRQ_UPHY * - * See <mach-t186/system-t186.h> + * Used by the sender of an #MRQ_UPHY message to control UPHY Lane RX margining. + * The uphy_request is split into several sub-commands. Some sub-commands + * require no additional data. Others have a sub-command specific payload * - * 4.3 System low power state enumerations + * |sub-command |payload | + * |------------------------------------ |----------------------------------------| + * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL |uphy_set_margin_control | + * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS | | + * |CMD_UPHY_PCIE_EP_CONTROLLER_PLL_INIT |cmd_uphy_ep_controller_pll_init_request | + * |CMD_UPHY_PCIE_CONTROLLER_STATE |cmd_uphy_pcie_controller_state_request | * - * See <mach-t186/system-t186.h> */ -/* - * 4.4 Clock enumerations +struct mrq_uphy_request { + /** @brief Lane number. */ + uint16_t lane; + /** @brief Sub-command id. */ + uint16_t cmd; + + union { + struct cmd_uphy_margin_control_request uphy_set_margin_control; + struct cmd_uphy_ep_controller_pll_init_request ep_ctrlr_pll_init; + struct cmd_uphy_pcie_controller_state_request controller_state; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup UPHY + * @brief Response to MRQ_UPHY + * + * Each sub-command supported by @ref mrq_uphy_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |---------------------------- |------------------------| + * |CMD_UPHY_PCIE_LANE_MARGIN_CONTROL | | + * |CMD_UPHY_PCIE_LANE_MARGIN_STATUS |uphy_get_margin_status | * - * For clock enumerations, see <mach-t186/clk-t186.h> */ -/* - * 4.5 Reset enumerations +struct mrq_uphy_response { + union { + struct cmd_uphy_margin_status_response uphy_get_margin_status; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_FMON + * @brief Perform a frequency monitor configuration operations + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_fmon_request + * * Response Payload: @ref mrq_fmon_response * - * For reset enumerations, see <mach-t186/reset-t186.h> + * @addtogroup FMON + * @{ */ +enum { + /** + * @brief Clamp FMON configuration to specified rate. + * + * The monitored clock must be running for clamp to succeed. If + * clamped, FMON configuration is preserved when clock rate + * and/or state is changed. + */ + CMD_FMON_GEAR_CLAMP = 1, + /** + * @brief Release clamped FMON configuration. + * + * Allow FMON configuration to follow monitored clock rate + * and/or state changes. + */ + CMD_FMON_GEAR_FREE = 2, + /** + * @brief Return rate FMON is clamped at, or 0 if FMON is not + * clamped. + * + * Inherently racy, since clamp state can be changed + * concurrently. Useful for testing. + */ + CMD_FMON_GEAR_GET = 3, + CMD_FMON_NUM, +}; -/* - * 4.6 Thermal sensor enumerations +struct cmd_fmon_gear_clamp_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_clamp_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_free_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_free_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_fmon_gear_get_request { + EMPTY +} __ABI_PACKED; + +struct cmd_fmon_gear_get_response { + int64_t rate; +} __ABI_PACKED; + +/** + * @ingroup FMON + * @brief Request with #MRQ_FMON + * + * Used by the sender of an #MRQ_FMON message to configure clock + * frequency monitors. The FMON request is split into several + * sub-commands. Some sub-commands require no additional data. + * Others have a sub-command specific payload + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |CMD_FMON_GEAR_CLAMP |fmon_gear_clamp | + * |CMD_FMON_GEAR_FREE |- | + * |CMD_FMON_GEAR_GET |- | + * + */ + +struct mrq_fmon_request { + /** @brief Sub-command and clock id concatenated to 32-bit word. + * - bits[31..24] is the sub-cmd. + * - bits[23..0] is monitored clock id used to select target + * FMON + */ + uint32_t cmd_and_id; + + union { + struct cmd_fmon_gear_clamp_request fmon_gear_clamp; + /** @private */ + struct cmd_fmon_gear_free_request fmon_gear_free; + /** @private */ + struct cmd_fmon_gear_get_request fmon_gear_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup FMON + * @brief Response to MRQ_FMON + * + * Each sub-command supported by @ref mrq_fmon_request may + * return sub-command-specific data as indicated below. + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |CMD_FMON_GEAR_CLAMP |- | + * |CMD_FMON_GEAR_FREE |- | + * |CMD_FMON_GEAR_GET |fmon_gear_get | + * + */ + +struct mrq_fmon_response { + union { + /** @private */ + struct cmd_fmon_gear_clamp_response fmon_gear_clamp; + /** @private */ + struct cmd_fmon_gear_free_response fmon_gear_free; + struct cmd_fmon_gear_get_response fmon_gear_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EC + * @brief Provide status information on faults reported by Error + * Collator (EC) to HSM. + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_ec_request + * * Response Payload: @ref mrq_ec_response + * + * @note This MRQ ABI is under construction, and subject to change + * + * @addtogroup EC + * @{ + */ +enum { + /** + * @brief Retrieve specified EC status. + * + * mrq_response::err is 0 if the operation was successful, or @n + * -#BPMP_ENODEV if target EC is not owned by BPMP @n + * -#BPMP_EACCES if target EC power domain is turned off + */ + CMD_EC_STATUS_GET = 1, + CMD_EC_NUM, +}; + +/** @brief BPMP ECs error types */ +enum bpmp_ec_err_type { + /** @brief Parity error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_PARITY_INTERNAL = 1, + + /** @brief ECC SEC error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_ECC_SEC_INTERNAL = 2, + + /** @brief ECC DED error on internal data path + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_ECC_DED_INTERNAL = 3, + + /** @brief Comparator error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_COMPARATOR = 4, + + /** @brief Register parity error + * + * Error descriptor @ref ec_err_reg_parity_desc. + */ + EC_ERR_TYPE_REGISTER_PARITY = 5, + + /** @brief Parity error from on-chip SRAM/FIFO + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_PARITY_SRAM = 6, + + /** @brief Clock Monitor error + * + * Error descriptor @ref ec_err_fmon_desc. + */ + EC_ERR_TYPE_CLOCK_MONITOR = 9, + + /** @brief Voltage Monitor error + * + * Error descriptor @ref ec_err_vmon_desc. + */ + EC_ERR_TYPE_VOLTAGE_MONITOR = 10, + + /** @brief SW Correctable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_SW_CORRECTABLE = 16, + + /** @brief SW Uncorrectable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_SW_UNCORRECTABLE = 17, + + /** @brief Other HW Correctable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_OTHER_HW_CORRECTABLE = 32, + + /** @brief Other HW Uncorrectable error + * + * Error descriptor @ref ec_err_simple_desc. + */ + EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE = 33, +}; + +/** @brief Group of registers with parity error. */ +enum ec_registers_group { + /** @brief Functional registers group */ + EC_ERR_GROUP_FUNC_REG = 0, + /** @brief SCR registers group */ + EC_ERR_GROUP_SCR_REG = 1, +}; + +/** + * @defgroup bpmp_ec_status_flags EC Status Flags + * @addtogroup bpmp_ec_status_flags + * @{ + */ +/** @brief No EC error found flag */ +#define EC_STATUS_FLAG_NO_ERROR 0x0001 +/** @brief Last EC error found flag */ +#define EC_STATUS_FLAG_LAST_ERROR 0x0002 +/** @brief EC latent error flag */ +#define EC_STATUS_FLAG_LATENT_ERROR 0x0004 +/** @} */ + +/** + * @defgroup bpmp_ec_desc_flags EC Descriptor Flags + * @addtogroup bpmp_ec_desc_flags + * @{ + */ +/** @brief EC descriptor error resolved flag */ +#define EC_DESC_FLAG_RESOLVED 0x0001 +/** @brief EC descriptor failed to retrieve id flag */ +#define EC_DESC_FLAG_NO_ID 0x0002 +/** @} */ + +/** + * |error type | fmon_clk_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_CLOCK_MONITOR |@ref bpmp_clock_ids | + */ +struct ec_err_fmon_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief FMON monitored clock id */ + uint16_t fmon_clk_id; + /** @brief Bitmask of @ref bpmp_fmon_faults_flags */ + uint32_t fmon_faults; + /** @brief FMON faults access error */ + int32_t fmon_access_error; +} __ABI_PACKED; + +/** + * |error type | vmon_adc_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_VOLTAGE_MONITOR |@ref bpmp_adc_ids | + */ +struct ec_err_vmon_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief VMON rail adc id */ + uint16_t vmon_adc_id; + /** @brief Bitmask of @ref bpmp_vmon_faults_flags */ + uint32_t vmon_faults; + /** @brief VMON faults access error */ + int32_t vmon_access_error; +} __ABI_PACKED; + +/** + * |error type | reg_id values | + * |---------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_REGISTER_PARITY |@ref bpmp_ec_registers_ids | + */ +struct ec_err_reg_parity_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief Register id */ + uint16_t reg_id; + /** @brief Register group @ref ec_registers_group */ + uint16_t reg_group; +} __ABI_PACKED; + +/** + * |error type | err_source_id values | + * |----------------------------------------|---------------------------| + * |@ref EC_ERR_TYPE_PARITY_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_SEC_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_ECC_DED_INTERNAL |@ref bpmp_ec_ipath_ids | + * |@ref EC_ERR_TYPE_COMPARATOR |@ref bpmp_ec_comparator_ids| + * |@ref EC_ERR_TYPE_PARITY_SRAM |@ref bpmp_clock_ids | + * |@ref EC_ERR_TYPE_SW_CORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_SW_UNCORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_CORRECTABLE |@ref bpmp_ec_misc_ids | + * |@ref EC_ERR_TYPE_OTHER_HW_UNCORRECTABLE |@ref bpmp_ec_misc_ids | + */ +struct ec_err_simple_desc { + /** @brief Bitmask of @ref bpmp_ec_desc_flags */ + uint16_t desc_flags; + /** @brief Error source id. Id space depends on error type. */ + uint16_t err_source_id; +} __ABI_PACKED; + +/** @brief Union of EC error descriptors */ +union ec_err_desc { + struct ec_err_fmon_desc fmon_desc; + struct ec_err_vmon_desc vmon_desc; + struct ec_err_reg_parity_desc reg_parity_desc; + struct ec_err_simple_desc simple_desc; +} __ABI_PACKED; + +struct cmd_ec_status_get_request { + /** @brief HSM error line number that identifies target EC. */ + uint32_t ec_hsm_id; +} __ABI_PACKED; + +/** EC status maximum number of descriptors */ +#define EC_ERR_STATUS_DESC_MAX_NUM 4 + +struct cmd_ec_status_get_response { + /** @brief Target EC id (the same id received with request). */ + uint32_t ec_hsm_id; + /** + * @brief Bitmask of @ref bpmp_ec_status_flags + * + * If NO_ERROR flag is set, error_ fields should be ignored + */ + uint32_t ec_status_flags; + /** @brief Found EC error index. */ + uint32_t error_idx; + /** @brief Found EC error type @ref bpmp_ec_err_type. */ + uint32_t error_type; + /** @brief Number of returned EC error descriptors */ + uint32_t error_desc_num; + /** @brief EC error descriptors */ + union ec_err_desc error_descs[EC_ERR_STATUS_DESC_MAX_NUM]; +} __ABI_PACKED; + +/** + * @ingroup EC + * @brief Request with #MRQ_EC + * + * Used by the sender of an #MRQ_EC message to access ECs owned + * by BPMP. + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |@ref CMD_EC_STATUS_GET |ec_status_get | * - * For thermal sensor enumerations, see <mach-t186/thermal-t186.h> */ +struct mrq_ec_request { + /** @brief Sub-command id. */ + uint32_t cmd_id; + + union { + struct cmd_ec_status_get_request ec_status_get; + } __UNION_ANON; +} __ABI_PACKED; + /** - * @defgroup Error_Codes + * @ingroup EC + * @brief Response to MRQ_EC + * + * Each sub-command supported by @ref mrq_ec_request may return + * sub-command-specific data as indicated below. + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |@ref CMD_EC_STATUS_GET |ec_status_get | + * + */ + +struct mrq_ec_response { + union { + struct cmd_ec_status_get_response ec_status_get; + } __UNION_ANON; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_FBVOLT_STATUS + * @brief Provides status information about voltage state for fuse burning + * + * * Platforms: T194 onwards + * @cond bpmp_t194 + * * Initiators: CCPLEX + * * Target: BPMP + * * Request Payload: None + * * Response Payload: @ref mrq_fbvolt_status_response + * @{ + */ + +/** + * @ingroup Fbvolt_status + * @brief Response to #MRQ_FBVOLT_STATUS + * + * Value of #ready reflects if core voltages are in a suitable state for buring + * fuses. A value of 0x1 indicates that core voltages are ready for burning + * fuses. A value of 0x0 indicates that core voltages are not ready. + */ +struct mrq_fbvolt_status_response { + /** @brief Bit [0:0] - ready status, bits [31:1] - reserved */ + uint32_t ready; + /** @brief Reserved */ + uint32_t unused; +} __ABI_PACKED; + +/** @} */ +/** @endcond */ + +/** + * @addtogroup Error_Codes * Negative values for mrq_response::err generally indicate some * error. The ABI defines the following error codes. Negating these * defines is an exercise left to the user. * @{ */ + /** @brief No such file or directory */ #define BPMP_ENOENT 2 /** @brief No MRQ handler */ @@ -1994,6 +2695,11 @@ union mrq_ringbuf_console_bpmp_to_host_response { #define BPMP_ETIMEDOUT 23 /** @brief Out of range */ #define BPMP_ERANGE 34 +/** @brief Function not implemented */ +#define BPMP_ENOSYS 38 +/** @brief Invalid slot */ +#define BPMP_EBADSLT 57 + /** @} */ -/** @} */ + #endif diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h index e69e4c4d80ae..b02f926a0216 100644 --- a/include/soc/tegra/bpmp.h +++ b/include/soc/tegra/bpmp.h @@ -129,6 +129,7 @@ int tegra_bpmp_request_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, tegra_bpmp_mrq_handler_t handler, void *data); void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data); +bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, unsigned int mrq); #else static inline struct tegra_bpmp *tegra_bpmp_get(struct device *dev) { @@ -164,6 +165,12 @@ static inline void tegra_bpmp_free_mrq(struct tegra_bpmp *bpmp, unsigned int mrq, void *data) { } + +static inline bool tegra_bpmp_mrq_is_supported(struct tegra_bpmp *bpmp, + unsigned int mrq) +{ + return false; +} #endif #if IS_ENABLED(CONFIG_CLK_TEGRA_BPMP) diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 9b6ea0c72117..8fb2f8a87339 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -60,7 +60,6 @@ struct tegra_sku_info { u32 tegra_read_straps(void); u32 tegra_read_ram_code(void); -u32 tegra_read_chipid(void); int tegra_fuse_readl(unsigned long offset, u32 *value); extern struct tegra_sku_info tegra_sku_info; diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 562426812ab2..fd816f6aa9cc 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -90,6 +90,10 @@ enum tegra_io_pad { TEGRA_IO_PAD_CSID, TEGRA_IO_PAD_CSIE, TEGRA_IO_PAD_CSIF, + TEGRA_IO_PAD_CSIG, + TEGRA_IO_PAD_CSIH, + TEGRA_IO_PAD_DAP3, + TEGRA_IO_PAD_DAP5, TEGRA_IO_PAD_DBG, TEGRA_IO_PAD_DEBUG_NONAO, TEGRA_IO_PAD_DMIC, @@ -102,10 +106,15 @@ enum tegra_io_pad { TEGRA_IO_PAD_EDP, TEGRA_IO_PAD_EMMC, TEGRA_IO_PAD_EMMC2, + TEGRA_IO_PAD_EQOS, TEGRA_IO_PAD_GPIO, + TEGRA_IO_PAD_GP_PWM2, + TEGRA_IO_PAD_GP_PWM3, TEGRA_IO_PAD_HDMI, TEGRA_IO_PAD_HDMI_DP0, TEGRA_IO_PAD_HDMI_DP1, + TEGRA_IO_PAD_HDMI_DP2, + TEGRA_IO_PAD_HDMI_DP3, TEGRA_IO_PAD_HSIC, TEGRA_IO_PAD_HV, TEGRA_IO_PAD_LVDS, @@ -115,8 +124,14 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_BIAS, TEGRA_IO_PAD_PEX_CLK1, TEGRA_IO_PAD_PEX_CLK2, + TEGRA_IO_PAD_PEX_CLK2_BIAS, TEGRA_IO_PAD_PEX_CLK3, TEGRA_IO_PAD_PEX_CNTRL, + TEGRA_IO_PAD_PEX_CTL2, + TEGRA_IO_PAD_PEX_L0_RST_N, + TEGRA_IO_PAD_PEX_L1_RST_N, + TEGRA_IO_PAD_PEX_L5_RST_N, + TEGRA_IO_PAD_PWR_CTL, TEGRA_IO_PAD_SDMMC1, TEGRA_IO_PAD_SDMMC1_HV, TEGRA_IO_PAD_SDMMC2, @@ -124,10 +139,16 @@ enum tegra_io_pad { TEGRA_IO_PAD_SDMMC3, TEGRA_IO_PAD_SDMMC3_HV, TEGRA_IO_PAD_SDMMC4, + TEGRA_IO_PAD_SOC_GPIO10, + TEGRA_IO_PAD_SOC_GPIO12, + TEGRA_IO_PAD_SOC_GPIO13, + TEGRA_IO_PAD_SOC_GPIO53, TEGRA_IO_PAD_SPI, TEGRA_IO_PAD_SPI_HV, TEGRA_IO_PAD_SYS_DDC, TEGRA_IO_PAD_UART, + TEGRA_IO_PAD_UART4, + TEGRA_IO_PAD_UART5, TEGRA_IO_PAD_UFS, TEGRA_IO_PAD_USB0, TEGRA_IO_PAD_USB1, |