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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-29 04:21:20 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-29 04:21:20 +0400 |
| commit | 56a50adda49b2020156616c4eb15353e0f9ad7de (patch) | |
| tree | a0453fde37538653628270258c3291d880a66853 /include | |
| parent | c2e2ceeae4b5587d412c05cdc31513179d37811d (diff) | |
| parent | 355d7f370b51bbb6f31aaf9f98861057e1e6bbb2 (diff) | |
| download | linux-56a50adda49b2020156616c4eb15353e0f9ad7de.tar.xz | |
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: fix up error path leak in i915_cmdbuffer
drm/i915: fix unpaired i915 device mutex on entervt failure.
drm/i915: add support for G41 chipset
drm/i915: Enable ASLE if present
drm/i915: Unregister ACPI video driver when exiting
drm/i915: Register ACPI video even when not modesetting
drm/i915: fix transition to I915_TILING_NONE
drm/i915: Don't let an oops get triggered from irq_emit without dma init.
drm/i915: allow tiled front buffers on 965+
Diffstat (limited to 'include')
| -rw-r--r-- | include/acpi/video.h | 2 | ||||
| -rw-r--r-- | include/drm/drm_pciids.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/include/acpi/video.h b/include/acpi/video.h index f0275bb79ce4..af6fe95fd3d0 100644 --- a/include/acpi/video.h +++ b/include/acpi/video.h @@ -3,8 +3,10 @@ #if (defined CONFIG_ACPI_VIDEO || defined CONFIG_ACPI_VIDEO_MODULE) extern int acpi_video_register(void); +extern int acpi_video_exit(void); #else static inline int acpi_video_register(void) { return 0; } +static inline void acpi_video_exit(void) { return; } #endif #endif diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index 9477af01a639..fc55db780199 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h @@ -532,6 +532,7 @@ {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ + {0x8086, 0x2e32, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ |