diff options
| author | Cliff Wickman <cpw@sgi.com> | 2008-08-19 21:51:59 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-08-20 14:36:03 +0400 |
| commit | 99dd8713306a89f3e106143581244e550e00a644 (patch) | |
| tree | 32581d2ce9374b1b6db33a2eec0a5c0bf626b1dc /include | |
| parent | 80c5e73d6028e0f03ab0c70e7c4cbf98ac2e0c43 (diff) | |
| download | linux-99dd8713306a89f3e106143581244e550e00a644.tar.xz | |
x86, SGI UV: hardcode the TLB flush interrupt system vector
The UV TLB shootdown mechanism needs a system interrupt vector.
Its vector had been hardcoded as 200, but needs to moved to the reserved
system vector range so that it does not collide with some device vector.
This is still temporary until dynamic system IRQ allocation is provided.
But it will be needed when real UV hardware becomes available and runs 2.6.27.
Signed-off-by: Cliff Wickman <cpw@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86/irq_vectors.h | 1 | ||||
| -rw-r--r-- | include/asm-x86/uv/uv_bau.h | 5 |
2 files changed, 1 insertions, 5 deletions
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h index b95d167b7fb2..a48c7f2dbdc0 100644 --- a/include/asm-x86/irq_vectors.h +++ b/include/asm-x86/irq_vectors.h @@ -76,6 +76,7 @@ #define CALL_FUNCTION_SINGLE_VECTOR 0xfb #define THERMAL_APIC_VECTOR 0xfa #define THRESHOLD_APIC_VECTOR 0xf9 +#define UV_BAU_MESSAGE 0xf8 #define INVALIDATE_TLB_VECTOR_END 0xf7 #define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */ diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h index 91ac0dfb7588..610b6b308e93 100644 --- a/include/asm-x86/uv/uv_bau.h +++ b/include/asm-x86/uv/uv_bau.h @@ -40,11 +40,6 @@ #define UV_ACTIVATION_DESCRIPTOR_SIZE 32 #define UV_DISTRIBUTION_SIZE 256 #define UV_SW_ACK_NPENDING 8 -#define UV_BAU_MESSAGE 200 -/* - * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h - * To be dynamically allocated in the future - */ #define UV_NET_ENDPOINT_INTD 0x38 #define UV_DESC_BASE_PNODE_SHIFT 49 #define UV_PAYLOADQ_PNODE_SHIFT 49 |