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| author | Michael Ellerman <mpe@ellerman.id.au> | 2025-03-16 04:02:46 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2025-03-16 04:02:46 +0300 |
| commit | ff443fb402e95f5095dde3c64f7c3249d7c6f993 (patch) | |
| tree | fac700d27838ff41a7308dc217551253a1e2b0df /include/uapi | |
| parent | 772ba9b5bd2701a9967c084b66ff1daaee0367eb (diff) | |
| parent | eff2eb592efd73f00590d578c3d6021f604df62c (diff) | |
| download | linux-ff443fb402e95f5095dde3c64f7c3249d7c6f993.tar.xz | |
Merge branch 'fixes' into topic/cxl
Merge our fixes branch to bring in the changes to the CXL documentation that
the CXL removal patch depends on.
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/drm/amdgpu_drm.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index efe5de6ce208..aaa4f3bc688b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -411,13 +411,20 @@ struct drm_amdgpu_gem_userptr { /* GFX12 and later: */ #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 #define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 -/* These are DCC recompression setting for memory management: */ +/* These are DCC recompression settings for memory management: */ #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 #define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 #define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 #define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ +/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata + * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */ +#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14 +#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1 +/* bit gap */ +#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63 +#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1 /* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) \ |