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authorKeith Busch <keith.busch@intel.com>2016-05-02 23:10:31 +0300
committerBjorn Helgaas <bhelgaas@google.com>2016-05-03 18:35:49 +0300
commit10126ac14d36e74b2705802dc915b0b18463a51f (patch)
tree9cff4695f03085209d3ebf71ecfdc1cd50054756 /include/uapi/linux/pci_regs.h
parent6d81417da8720b393f670de9cce03a3642ea9a30 (diff)
downloadlinux-10126ac14d36e74b2705802dc915b0b18463a51f.tar.xz
PCI: Add Downstream Port Containment portdrv service type
Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service type, available if the device has the DPC extended capability. [bhelgaas: split to separate patch, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
-rw-r--r--include/uapi/linux/pci_regs.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 1becea86c73c..61e95c142547 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -670,7 +670,8 @@
#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
-#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
+#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC
#define PCI_EXT_CAP_DSN_SIZEOF 12
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40