diff options
| author | Frederick Lawler <fred@fredlawl.com> | 2018-04-17 03:28:24 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-04-27 20:51:47 +0300 |
| commit | c80851f6ce63a6e313f8c7b4b6eb82c67aa4497b (patch) | |
| tree | 31edd2712d2e1820d87b2cedf53a196c1c9962a3 /include/uapi/linux/pci_regs.h | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
| download | linux-c80851f6ce63a6e313f8c7b4b6eb82c67aa4497b.tar.xz | |
PCI: Add PCI_EXP_LNKCTL2_TLS* macros
The Link Control 2 register is missing macros for Target Link Speeds. Add
those in.
Signed-off-by: Frederick Lawler <fred@fredlawl.com>
[bhelgaas: use "GT" instead of "GB"]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 103ba797a8f3..d9885db3b43a 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -655,6 +655,11 @@ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +#define PCI_EXP_LNKCTL2_TLS 0x000f +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |