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author | Mark Brown <broonie@kernel.org> | 2022-04-19 14:22:29 +0300 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-04-22 20:51:17 +0300 |
commit | 776b4a1cf36411e96972455ca72906b722b80ea1 (patch) | |
tree | d753694ef8a1b64c74902c57320d03807a79d7a4 /include/uapi/linux/elf.h | |
parent | e12310a0d30f260b26297bc8d7c95769489af038 (diff) | |
download | linux-776b4a1cf36411e96972455ca72906b722b80ea1.tar.xz |
arm64/sme: Add ptrace support for ZA
The ZA array can be read and written with the NT_ARM_ZA. Similarly to
our interface for the SVE vector registers the regset consists of a
header with information on the current vector length followed by an
optional register data payload, represented as for signals as a series
of horizontal vectors from 0 to VL/8 in the endianness independent
format used for vectors.
On get if ZA is enabled then register data will be provided, otherwise
it will be omitted. On set if register data is provided then ZA is
enabled and initialized using the provided data, otherwise it is
disabled.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419112247.711548-22-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'include/uapi/linux/elf.h')
-rw-r--r-- | include/uapi/linux/elf.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index a8dc688e1826..97808f958903 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -432,6 +432,7 @@ typedef struct elf64_shdr { #define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* arm64 tagged address control (prctl()) */ #define NT_ARM_PAC_ENABLED_KEYS 0x40a /* arm64 ptr auth enabled keys (prctl()) */ #define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers */ +#define NT_ARM_ZA 0x40c /* ARM SME ZA registers */ #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */ #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */ #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ |