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authorMarek Olšák <marek.olsak@amd.com>2019-01-22 01:22:55 +0300
committerAlex Deucher <alexander.deucher@amd.com>2019-02-06 05:15:46 +0300
commit41cca166cc57e75e94d888595a428d23a3bf4e36 (patch)
treef9c01b66358ac82def807ca7074c501bccd718e9 /include/uapi/drm
parent67dd1a36334ffce82bebeb2d633e152aa436d370 (diff)
downloadlinux-41cca166cc57e75e94d888595a428d23a3bf4e36.tar.xz
drm/amdgpu: add a workaround for GDS ordered append hangs with compute queues
I'm not increasing the DRM version because GDS isn't totally without bugs yet. v2: update emit_ib_size Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/amdgpu_drm.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 47296f2ec3fa..2acbc8bc465b 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -566,6 +566,11 @@ union drm_amdgpu_cs {
* caches (L2/vL1/sL1/I$). */
#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
+ * This will reset wave ID counters for the IB.
+ */
+#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
+
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */