Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Not a ton of stuff happening in the clk framework. We got some more
  devm helpers and we seem to be going in the direction of "just turn
  this stuff on already and leave me alone!" with the addition of a
  devm_clk_bulk_get_all_enable() API. I'm hoping that we can make that
  into a pmdomain that drivers attach instead, but this API should help
  drivers simplify in the meantime.

  Outside of the devm wrappers, we've got the usual clk driver updates
  that are dominated by the major phone SoC vendors (Samsung and
  Qualcomm) and the non-critical driver fixes for things like incorrect
  topology descriptions and wrong registers or bit fields. More details
  are below, but I'd say that it looks pretty ordinary. The only thing
  that really jumps out at me is the Renesas clk driver that's ignoring
  clks that are assigned to remote processors in DeviceTree. That's a
  new feature that they're using to avoid marking clks as
  CLK_IGNORE_UNUSED based on the configuration of the system.

  Core:
   - Increase dev_id len for clkdev lookups
   - Add a devm_clk_bulk_get_all_enable() API to get and enable all clks
     for a device
   - Add a devm variant of clk_rate_exclusive_get()

  New Drivers:
   - Display, TCSR, GPU, and Camera clock controllers for Qualcomm's X1
     Elite SoC
   - Google GS101 PERIC0 and PERIC1 clock controllers
   - Exynos850 PDMA clocks
   - Exynos850 CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock
     controllers

  Removed Drivers:
   - Remove the unused Qualcomm sc7180 modem clk driver

  Updates:
   - Fix some static checker errors in the Hisilicon clk driver
   - Polarfire MSSPLL hardware has 4 output clocks (the driver supported
     previously only one output); each of these 4 outputs feed dividers
     and the output of each divider feed individual hardware blocks
     (e.g. CAN, Crypto, eMMC); individual hardware block drivers need to
     control their clocks thus clock driver support was added for all
     MSSPLL output clocks
   - Typo fixes in the Qualcomm IPQ5018 GCC driver
   - Add "qdss_at" clk on Qualcomm IPQ6018, needed for WiFi
   - Properly terminate frequency tables in different Qualcomm clk
     drivers
   - Add MDSS, crypto, and SDCC resets on Qualcomm MSM8953
   - Add missing UFS CLKREF clks on Qualcomm SC8180X
   - Avoid significant delays during boot by adding a softdep on rpmhpd
     to Qualcomm SDM845 gcc driver
   - Add QUPv3 RCGS w/ DFS and video resets to Qualcomm SM8150 GCC
     driver
   - Fix the custom GPU GX "do-nothing" method in the Qualcomm GDSC
     driver
   - Add an external regulator to GX GDSC on Qualcomm SC8280XP GPU clk
     driver
   - Switch display, GPU, video, and camera Qualcomm clk drivers to
     module_platform_driver()
   - Set a longer delay for Venus resets on many Qualcomm SoCs
   - Correct the GDSC wait times in the Qualcomm SDM845 display clk
     driver
   - Fix clock listing Oops on Amlogic axg
   - New pll-rate for Rockchip rk3568
   - i2s rate improvements for Rockchip rk3399
   - Rockchip rk3588 syscon clock fixes and removal of overall
     clock-number from the rk3588 binding header
   - A prerequisite for later improvements to the Rockchip rk3588 linked
     clocks
   - Minor clean-ups and error handling improvements in both
     composite-8m and SCU i.MX clock drivers
   - Fix for SAI_MCLK_SEL definition for i.MX8MP
   - Register the Samsung CMU MISC clock controller earlier, so the
     Multi Core Timer clocksource can use it on Google GS101
   - Propagate Exynos850 SPI IPCLK rate change to parents, so the SPI
     will get proper clock rates
   - Refactor the generic Samsung CPU clock controllers code, preparing
     it for supporting Exynos850 CPU clocks
   - Fix some clk kerneldoc warnings
   - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on
     Renesas R-Car V4M
   - Ignore all clocks which are assigned to a non-Linux system in the
     Renesas clk driver
   - Add watchdog clock on Renesas RZ/G3S
   - Add camera (CRU) clock and reset on Renesas RZ/G2UL
   - Add support for the Renesas R-Car V4M (R8A779H0) SoC
   - Convert some clk bindings to YAML so they can be validated"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
  clk: zynq: Prevent null pointer dereference caused by kmalloc failure
  clk: fractional-divider: Use bit operations consistently
  clk: fractional-divider: Move mask calculations out of lock
  clk: Fix clk_core_get NULL dereference
  clk: starfive: jh7110-vout: Convert to platform remove callback returning void
  clk: starfive: jh7110-isp: Convert to platform remove callback returning void
  clk: imx: imx8-acm: Convert to platform remove callback returning void
  clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset
  clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk'
  clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk'
  clk: qcom: camcc-x1e80100: Fix missing DT_IFACE enum in x1e80100 camcc
  clk: qcom: mmcc-msm8974: fix terminating of frequency table arrays
  clk: qcom: mmcc-apq8084: fix terminating of frequency table arrays
  clk: qcom: camcc-sc8280xp: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq9574: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq8074: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq6018: fix terminating of frequency table arrays
  clk: qcom: gcc-ipq5018: fix terminating of frequency table arrays
  clk: mediatek: clk-mt8173-apmixedsys: Use common error handling code in clk_mt8173_apmixed_probe()
  clk: Add a devm variant of clk_rate_exclusive_get()
  ...

3 files changed, 70 insertions, 1 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 1293c38ddb7f..4a537260f655 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1084,18 +1084,28 @@ void of_fixed_factor_clk_setup(struct device_node *node);
  * @hw:		handle between common and hardware-specific interfaces
  * @mult:	multiplier
  * @div:	divider
+ * @acc:	fixed accuracy in ppb
+ * @flags:	behavior modifying flags
  *
  * Clock with a fixed multiplier and divider. The output frequency is the
  * parent clock rate divided by div and multiplied by mult.
- * Implements .recalc_rate, .set_rate and .round_rate
+ * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy
+ *
+ * Flags:
+ * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
+ *                                     parent clk accuracy.
  */
 
 struct clk_fixed_factor {
 	struct clk_hw	hw;
 	unsigned int	mult;
 	unsigned int	div;
+	unsigned long	acc;
+	unsigned int	flags;
 };
 
+#define CLK_FIXED_FACTOR_FIXED_ACCURACY	BIT(0)
+
 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
 
 extern const struct clk_ops clk_fixed_factor_ops;
@@ -1106,10 +1116,24 @@ void clk_unregister_fixed_factor(struct clk *clk);
 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
 		const char *name, const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
+struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
+		struct device_node *np, const char *name, const char *fw_name,
+		unsigned long flags, unsigned int mult, unsigned int div);
+struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
+		struct device_node *np, const char *name, const char *fw_name,
+		unsigned long flags, unsigned int mult, unsigned int div,
+		unsigned long acc);
 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
 		const char *name, const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
+struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
+		struct device_node *np, const char *name, const char *fw_name,
+		unsigned long flags, unsigned int mult, unsigned int div);
+struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
+		struct device_node *np, const char *name, const char *fw_name,
+		unsigned long flags, unsigned int mult, unsigned int div,
+		unsigned long acc);
 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
 		const char *name, unsigned int index, unsigned long flags,
 		unsigned int mult, unsigned int div);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 06f1b292f8a0..00623f4de5e1 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -202,6 +202,18 @@ bool clk_is_match(const struct clk *p, const struct clk *q);
 int clk_rate_exclusive_get(struct clk *clk);
 
 /**
+ * devm_clk_rate_exclusive_get - devm variant of clk_rate_exclusive_get
+ * @dev: device the exclusivity is bound to
+ * @clk: clock source
+ *
+ * Calls clk_rate_exclusive_get() on @clk and registers a devm cleanup handler
+ * on @dev to call clk_rate_exclusive_put().
+ *
+ * Must not be called from within atomic context.
+ */
+int devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk);
+
+/**
  * clk_rate_exclusive_put - release exclusivity over the rate control of a
  *                          producer
  * @clk: clock source
@@ -479,6 +491,22 @@ int __must_check devm_clk_bulk_get_all(struct device *dev,
 				       struct clk_bulk_data **clks);
 
 /**
+ * devm_clk_bulk_get_all_enable - Get and enable all clocks of the consumer (managed)
+ * @dev: device for clock "consumer"
+ * @clks: pointer to the clk_bulk_data table of consumer
+ *
+ * Returns success (0) or negative errno.
+ *
+ * This helper function allows drivers to get all clocks of the
+ * consumer and enables them in one operation with management.
+ * The clks will automatically be disabled and freed when the device
+ * is unbound.
+ */
+
+int __must_check devm_clk_bulk_get_all_enable(struct device *dev,
+					      struct clk_bulk_data **clks);
+
+/**
  * devm_clk_get - lookup and obtain a managed reference to a clock producer.
  * @dev: device for clock "consumer"
  * @id: clock consumer ID
@@ -968,6 +996,12 @@ static inline int __must_check devm_clk_bulk_get_all(struct device *dev,
 	return 0;
 }
 
+static inline int __must_check devm_clk_bulk_get_all_enable(struct device *dev,
+						struct clk_bulk_data **clks)
+{
+	return 0;
+}
+
 static inline struct clk *devm_get_clk_from_child(struct device *dev,
 				struct device_node *np, const char *con_id)
 {
diff --git a/include/linux/of.h b/include/linux/of.h
index 6a9ddf20e79a..331e05918f11 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -294,6 +294,8 @@ extern struct device_node *of_get_next_child(const struct device_node *node,
 					     struct device_node *prev);
 extern struct device_node *of_get_next_available_child(
 	const struct device_node *node, struct device_node *prev);
+extern struct device_node *of_get_next_reserved_child(
+	const struct device_node *node, struct device_node *prev);
 
 extern struct device_node *of_get_compatible_child(const struct device_node *parent,
 					const char *compatible);
@@ -541,6 +543,12 @@ static inline struct device_node *of_get_next_available_child(
 	return NULL;
 }
 
+static inline struct device_node *of_get_next_reserved_child(
+	const struct device_node *node, struct device_node *prev)
+{
+	return NULL;
+}
+
 static inline struct device_node *of_find_node_with_property(
 	struct device_node *from, const char *prop_name)
 {
@@ -1431,6 +1439,9 @@ static inline int of_property_read_s32(const struct device_node *np,
 #define for_each_available_child_of_node(parent, child) \
 	for (child = of_get_next_available_child(parent, NULL); child != NULL; \
 	     child = of_get_next_available_child(parent, child))
+#define for_each_reserved_child_of_node(parent, child)			\
+	for (child = of_get_next_reserved_child(parent, NULL); child != NULL; \
+	     child = of_get_next_reserved_child(parent, child))
 
 #define for_each_of_cpu_node(cpu) \
 	for (cpu = of_get_next_cpu_node(NULL); cpu != NULL; \