diff options
| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-06-08 18:47:17 +0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-06-16 07:23:36 +0400 |
| commit | ba492e900704ba00d43c7af9d94b00da4df52587 (patch) | |
| tree | 497484f3a3a8c796ccab042ba7be5a81e15d871b /include/linux | |
| parent | f3aab5d61400b794ec759b9345e93e7ba57eb369 (diff) | |
| download | linux-ba492e900704ba00d43c7af9d94b00da4df52587.tar.xz | |
clk: mux: add CLK_MUX_HIWORD_MASK
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.
When b01 should be set as switching mux, it also needs to indicate
the change by setting hiword mask (b11 << 16).
The patch adds mux flag for this usage.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/clk-provider.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 265f384f1e01..37ad97961e5a 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -299,6 +299,10 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) + * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this + * register, and mask of mux bits are in higher 16-bit of this register. + * While setting the mux bits, higher 16-bit should also be updated to + * indicate changing mux bits. */ struct clk_mux { struct clk_hw hw; @@ -312,6 +316,7 @@ struct clk_mux { #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) +#define CLK_MUX_HIWORD_MASK BIT(2) extern const struct clk_ops clk_mux_ops; |