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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-30 20:13:08 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-30 20:13:08 +0400
commit17d30ac077df253c12c7ba4db8d5cdacfceeb6d1 (patch)
tree991a18cd249d66c7e08faa1b93f014ad169f04f3 /include/linux
parente38c1e54ce51059a1aa8744c895762906cf43b32 (diff)
parent191211f50f35deb5b3b80bc7b620cfd4b0a4a2d9 (diff)
downloadlinux-17d30ac077df253c12c7ba4db8d5cdacfceeb6d1.tar.xz
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (47 commits) mfd: Rename twl5031 sih modules mfd: Storage class for timberdale should be before const qualifier mfd: Remove unneeded and dangerous clearing of clientdata mfd: New AB8500 driver gpio: Fix inverted rdc321x gpio data out registers mfd: Change rdc321x resources flags to IORESOURCE_IO mfd: Move pcf50633 irq related functions to its own file. mfd: Use threaded irq for pcf50633 mfd: pcf50633-adc: Fix potential race in pcf50633_adc_sync_read mfd: Fix pcf50633 bitfield logic in interrupt handler gpio: rdc321x needs to select MFD_CORE mfd: Use menuconfig for quicker config editing ARM: AB3550 board configuration and irq for U300 mfd: AB3550 core driver mfd: AB3100 register access change to abx500 API mfd: Renamed ab3100.h to abx500.h gpio: Add TC35892 GPIO driver mfd: Add Toshiba's TC35892 MFD core mfd: Delay to mask tsc irq in max8925 mfd: Remove incorrect wm8350 kfree ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/input/tps6507x-ts.h24
-rw-r--r--include/linux/mfd/88pm860x.h4
-rw-r--r--include/linux/mfd/ab4500.h262
-rw-r--r--include/linux/mfd/ab8500.h128
-rw-r--r--include/linux/mfd/abx500.h (renamed from include/linux/mfd/ab3100.h)134
-rw-r--r--include/linux/mfd/janz.h54
-rw-r--r--include/linux/mfd/rdc321x.h26
-rw-r--r--include/linux/mfd/tc35892.h132
-rw-r--r--include/linux/mfd/tps6507x.h169
-rw-r--r--include/linux/mfd/wm831x/core.h5
10 files changed, 657 insertions, 281 deletions
diff --git a/include/linux/input/tps6507x-ts.h b/include/linux/input/tps6507x-ts.h
new file mode 100644
index 000000000000..ab1440313924
--- /dev/null
+++ b/include/linux/input/tps6507x-ts.h
@@ -0,0 +1,24 @@
+/* linux/i2c/tps6507x-ts.h
+ *
+ * Functions to access TPS65070 touch screen chip.
+ *
+ * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
+ *
+ *
+ * For licencing details see kernel-base/COPYING
+ */
+
+#ifndef __LINUX_I2C_TPS6507X_TS_H
+#define __LINUX_I2C_TPS6507X_TS_H
+
+/* Board specific touch screen initial values */
+struct touchscreen_init_data {
+ int poll_period; /* ms */
+ int vref; /* non-zero to leave vref on */
+ __u16 min_pressure; /* min reading to be treated as a touch */
+ __u16 vendor;
+ __u16 product;
+ __u16 version;
+};
+
+#endif /* __LINUX_I2C_TPS6507X_TS_H */
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index e3c4ff8c3e38..bfd23bef7363 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -370,7 +370,7 @@ extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_device_init(struct pm860x_chip *chip,
- struct pm860x_platform_data *pdata);
-extern void pm860x_device_exit(struct pm860x_chip *chip);
+ struct pm860x_platform_data *pdata) __devinit ;
+extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
#endif /* __LINUX_MFD_88PM860X_H */
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
deleted file mode 100644
index a42a7033ae53..000000000000
--- a/include/linux/mfd/ab4500.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson
- *
- * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- *
- * AB4500 device core funtions, for client access
- */
-#ifndef MFD_AB4500_H
-#define MFD_AB4500_H
-
-#include <linux/device.h>
-
-/*
- * AB4500 bank addresses
- */
-#define AB4500_SYS_CTRL1_BLOCK 0x1
-#define AB4500_SYS_CTRL2_BLOCK 0x2
-#define AB4500_REGU_CTRL1 0x3
-#define AB4500_REGU_CTRL2 0x4
-#define AB4500_USB 0x5
-#define AB4500_TVOUT 0x6
-#define AB4500_DBI 0x7
-#define AB4500_ECI_AV_ACC 0x8
-#define AB4500_RESERVED 0x9
-#define AB4500_GPADC 0xA
-#define AB4500_CHARGER 0xB
-#define AB4500_GAS_GAUGE 0xC
-#define AB4500_AUDIO 0xD
-#define AB4500_INTERRUPT 0xE
-#define AB4500_RTC 0xF
-#define AB4500_MISC 0x10
-#define AB4500_DEBUG 0x12
-#define AB4500_PROD_TEST 0x13
-#define AB4500_OTP_EMUL 0x15
-
-/*
- * System control 1 register offsets.
- * Bank = 0x01
- */
-#define AB4500_TURNON_STAT_REG 0x0100
-#define AB4500_RESET_STAT_REG 0x0101
-#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
-
-#define AB4500_FSM_STAT1_REG 0x0140
-#define AB4500_FSM_STAT2_REG 0x0141
-#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
-#define AB4500_USB_STAT1_REG 0x0143
-#define AB4500_USB_STAT2_REG 0x0144
-#define AB4500_STATUS_SPARE1_REG 0x0145
-#define AB4500_STATUS_SPARE2_REG 0x0146
-
-#define AB4500_CTRL1_REG 0x0180
-#define AB4500_CTRL2_REG 0x0181
-
-/*
- * System control 2 register offsets.
- * bank = 0x02
- */
-#define AB4500_CTRL3_REG 0x0200
-#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
-#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
-#define AB4500_LOW_BAT_REG 0x0203
-#define AB4500_BATT_OK_REG 0x0204
-#define AB4500_SYSCLK_TIMER_REG 0x0205
-#define AB4500_SMPSCLK_CTRL_REG 0x0206
-#define AB4500_SMPSCLK_SEL1_REG 0x0207
-#define AB4500_SMPSCLK_SEL2_REG 0x0208
-#define AB4500_SMPSCLK_SEL3_REG 0x0209
-#define AB4500_SYSULPCLK_CONF_REG 0x020A
-#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
-#define AB4500_SYSCLK_CTRL_REG 0x020C
-#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
-#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
-#define AB4500_SYSCTRL_SPARE_REG 0x020F
-#define AB4500_PAD_CONF_REG 0x0210
-
-/*
- * Regu control1 register offsets
- * Bank = 0x03
- */
-#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
-#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
-#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
-#define AB4500_REGU_REQ_CTRL1_REG 0x0303
-#define AB4500_REGU_REQ_CTRL2_REG 0x0304
-#define AB4500_REGU_REQ_CTRL3_REG 0x0305
-#define AB4500_REGU_REQ_CTRL4_REG 0x0306
-#define AB4500_REGU_MISC1_REG 0x0380
-#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
-#define AB4500_REGU_VUSB_CTRL_REG 0x0382
-#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
-#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
-
-/*
- * Regu control2 Vmod register offsets
- */
-#define AB4500_REGU_VMOD_REGU_REG 0x0440
-#define AB4500_REGU_VMOD_SEL1_REG 0x0441
-#define AB4500_REGU_VMOD_SEL2_REG 0x0442
-#define AB4500_REGU_CTRL_DISCH_REG 0x0443
-#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
-
-/*
- * USB/ULPI register offsets
- * Bank : 0x5
- */
-#define AB4500_USB_LINE_STAT_REG 0x0580
-#define AB4500_USB_LINE_CTRL1_REG 0x0581
-#define AB4500_USB_LINE_CTRL2_REG 0x0582
-#define AB4500_USB_LINE_CTRL3_REG 0x0583
-#define AB4500_USB_LINE_CTRL4_REG 0x0584
-#define AB4500_USB_LINE_CTRL5_REG 0x0585
-#define AB4500_USB_OTG_CTRL_REG 0x0587
-#define AB4500_USB_OTG_STAT_REG 0x0588
-#define AB4500_USB_OTG_STAT_REG 0x0588
-#define AB4500_USB_CTRL_SPARE_REG 0x0589
-#define AB4500_USB_PHY_CTRL_REG 0x058A
-
-/*
- * TVOUT / CTRL register offsets
- * Bank : 0x06
- */
-#define AB4500_TVOUT_CTRL_REG 0x0680
-
-/*
- * DBI register offsets
- * Bank : 0x07
- */
-#define AB4500_DBI_REG1_REG 0x0700
-#define AB4500_DBI_REG2_REG 0x0701
-
-/*
- * ECI regsiter offsets
- * Bank : 0x08
- */
-#define AB4500_ECI_CTRL_REG 0x0800
-#define AB4500_ECI_HOOKLEVEL_REG 0x0801
-#define AB4500_ECI_DATAOUT_REG 0x0802
-#define AB4500_ECI_DATAIN_REG 0x0803
-
-/*
- * AV Connector register offsets
- * Bank : 0x08
- */
-#define AB4500_AV_CONN_REG 0x0840
-
-/*
- * Accessory detection register offsets
- * Bank : 0x08
- */
-#define AB4500_ACC_DET_DB1_REG 0x0880
-#define AB4500_ACC_DET_DB2_REG 0x0881
-
-/*
- * GPADC register offsets
- * Bank : 0x0A
- */
-#define AB4500_GPADC_CTRL1_REG 0x0A00
-#define AB4500_GPADC_CTRL2_REG 0x0A01
-#define AB4500_GPADC_CTRL3_REG 0x0A02
-#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
-#define AB4500_GPADC_STAT_REG 0x0A04
-#define AB4500_GPADC_MANDATAL_REG 0x0A05
-#define AB4500_GPADC_MANDATAH_REG 0x0A06
-#define AB4500_GPADC_AUTODATAL_REG 0x0A07
-#define AB4500_GPADC_AUTODATAH_REG 0x0A08
-#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
-
-/*
- * Charger / status register offfsets
- * Bank : 0x0B
- */
-#define AB4500_CH_STATUS1_REG 0x0B00
-#define AB4500_CH_STATUS2_REG 0x0B01
-#define AB4500_CH_USBCH_STAT1_REG 0x0B02
-#define AB4500_CH_USBCH_STAT2_REG 0x0B03
-#define AB4500_CH_FSM_STAT_REG 0x0B04
-#define AB4500_CH_STAT_REG 0x0B05
-
-/*
- * Charger / control register offfsets
- * Bank : 0x0B
- */
-#define AB4500_CH_VOLT_LVL_REG 0x0B40
-
-/*
- * Charger / main control register offfsets
- * Bank : 0x0B
- */
-#define AB4500_MCH_CTRL1 0x0B80
-#define AB4500_MCH_CTRL2 0x0B81
-#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
-#define AB4500_CH_WD_REG 0x0B83
-
-/*
- * Charger / USB control register offsets
- * Bank : 0x0B
- */
-#define AB4500_USBCH_CTRL1_REG 0x0BC0
-#define AB4500_USBCH_CTRL2_REG 0x0BC1
-#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
-
-/*
- * RTC bank register offsets
- * Bank : 0xF
- */
-#define AB4500_RTC_SOFF_STAT_REG 0x0F00
-#define AB4500_RTC_CC_CONF_REG 0x0F01
-#define AB4500_RTC_READ_REQ_REG 0x0F02
-#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
-#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
-#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
-#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
-#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
-#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
-#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
-#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
-#define AB4500_RTC_STAT_REG 0x0F0B
-#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
-#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
-#define AB4500_RTC_CALIB_REG 0x0F0E
-#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
-
-/*
- * PWM Out generators
- * Bank: 0x10
- */
-#define AB4500_PWM_OUT_CTRL1_REG 0x1060
-#define AB4500_PWM_OUT_CTRL2_REG 0x1061
-#define AB4500_PWM_OUT_CTRL3_REG 0x1062
-#define AB4500_PWM_OUT_CTRL4_REG 0x1063
-#define AB4500_PWM_OUT_CTRL5_REG 0x1064
-#define AB4500_PWM_OUT_CTRL6_REG 0x1065
-#define AB4500_PWM_OUT_CTRL7_REG 0x1066
-
-#define AB4500_I2C_PAD_CTRL_REG 0x1067
-#define AB4500_REV_REG 0x1080
-
-/**
- * struct ab4500
- * @spi: spi device structure
- * @tx_buf: transmit buffer
- * @rx_buf: receive buffer
- * @lock: sync primitive
- */
-struct ab4500 {
- struct spi_device *spi;
- unsigned long tx_buf[4];
- unsigned long rx_buf[4];
- struct mutex lock;
-};
-
-int ab4500_write(struct ab4500 *ab4500, unsigned char block,
- unsigned long addr, unsigned char data);
-int ab4500_read(struct ab4500 *ab4500, unsigned char block,
- unsigned long addr);
-
-#endif /* MFD_AB4500_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
new file mode 100644
index 000000000000..b63ff3ba3351
--- /dev/null
+++ b/include/linux/mfd/ab8500.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ */
+#ifndef MFD_AB8500_H
+#define MFD_AB8500_H
+
+#include <linux/device.h>
+
+/*
+ * Interrupts
+ */
+
+#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
+#define AB8500_INT_UN_PLUG_TV_DET 1
+#define AB8500_INT_PLUG_TV_DET 2
+#define AB8500_INT_TEMP_WARM 3
+#define AB8500_INT_PON_KEY2DB_F 4
+#define AB8500_INT_PON_KEY2DB_R 5
+#define AB8500_INT_PON_KEY1DB_F 6
+#define AB8500_INT_PON_KEY1DB_R 7
+#define AB8500_INT_BATT_OVV 8
+#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
+#define AB8500_INT_MAIN_CH_PLUG_DET 11
+#define AB8500_INT_USB_ID_DET_F 12
+#define AB8500_INT_USB_ID_DET_R 13
+#define AB8500_INT_VBUS_DET_F 14
+#define AB8500_INT_VBUS_DET_R 15
+#define AB8500_INT_VBUS_CH_DROP_END 16
+#define AB8500_INT_RTC_60S 17
+#define AB8500_INT_RTC_ALARM 18
+#define AB8500_INT_BAT_CTRL_INDB 20
+#define AB8500_INT_CH_WD_EXP 21
+#define AB8500_INT_VBUS_OVV 22
+#define AB8500_INT_MAIN_CH_DROP_END 23
+#define AB8500_INT_CCN_CONV_ACC 24
+#define AB8500_INT_INT_AUD 25
+#define AB8500_INT_CCEOC 26
+#define AB8500_INT_CC_INT_CALIB 27
+#define AB8500_INT_LOW_BAT_F 28
+#define AB8500_INT_LOW_BAT_R 29
+#define AB8500_INT_BUP_CHG_NOT_OK 30
+#define AB8500_INT_BUP_CHG_OK 31
+#define AB8500_INT_GP_HW_ADC_CONV_END 32
+#define AB8500_INT_ACC_DETECT_1DB_F 33
+#define AB8500_INT_ACC_DETECT_1DB_R 34
+#define AB8500_INT_ACC_DETECT_22DB_F 35
+#define AB8500_INT_ACC_DETECT_22DB_R 36
+#define AB8500_INT_ACC_DETECT_21DB_F 37
+#define AB8500_INT_ACC_DETECT_21DB_R 38
+#define AB8500_INT_GP_SW_ADC_CONV_END 39
+#define AB8500_INT_BTEMP_LOW 72
+#define AB8500_INT_BTEMP_LOW_MEDIUM 73
+#define AB8500_INT_BTEMP_MEDIUM_HIGH 74
+#define AB8500_INT_BTEMP_HIGH 75
+#define AB8500_INT_USB_CHARGER_NOT_OK 81
+#define AB8500_INT_ID_WAKEUP_R 82
+#define AB8500_INT_ID_DET_R1R 84
+#define AB8500_INT_ID_DET_R2R 85
+#define AB8500_INT_ID_DET_R3R 86
+#define AB8500_INT_ID_DET_R4R 87
+#define AB8500_INT_ID_WAKEUP_F 88
+#define AB8500_INT_ID_DET_R1F 90
+#define AB8500_INT_ID_DET_R2F 91
+#define AB8500_INT_ID_DET_R3F 92
+#define AB8500_INT_ID_DET_R4F 93
+#define AB8500_INT_USB_CHG_DET_DONE 94
+#define AB8500_INT_USB_CH_TH_PROT_F 96
+#define AB8500_INT_USB_CH_TH_PROP_R 97
+#define AB8500_INT_MAIN_CH_TH_PROP_F 98
+#define AB8500_INT_MAIN_CH_TH_PROT_R 99
+#define AB8500_INT_USB_CHARGER_NOT_OKF 103
+
+#define AB8500_NR_IRQS 104
+#define AB8500_NUM_IRQ_REGS 13
+
+/**
+ * struct ab8500 - ab8500 internal structure
+ * @dev: parent device
+ * @lock: read/write operations lock
+ * @irq_lock: genirq bus lock
+ * @revision: chip revision
+ * @irq: irq line
+ * @write: register write
+ * @read: register read
+ * @rx_buf: rx buf for SPI
+ * @tx_buf: tx buf for SPI
+ * @mask: cache of IRQ regs for bus lock
+ * @oldmask: cache of previous IRQ regs for bus lock
+ */
+struct ab8500 {
+ struct device *dev;
+ struct mutex lock;
+ struct mutex irq_lock;
+ int revision;
+ int irq_base;
+ int irq;
+
+ int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
+ int (*read) (struct ab8500 *a8500, u16 addr);
+
+ unsigned long tx_buf[4];
+ unsigned long rx_buf[4];
+
+ u8 mask[AB8500_NUM_IRQ_REGS];
+ u8 oldmask[AB8500_NUM_IRQ_REGS];
+};
+
+/**
+ * struct ab8500_platform_data - AB8500 platform data
+ * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
+ * @init: board-specific initialization after detection of ab8500
+ */
+struct ab8500_platform_data {
+ int irq_base;
+ void (*init) (struct ab8500 *);
+};
+
+extern int ab8500_write(struct ab8500 *a8500, u16 addr, u8 data);
+extern int ab8500_read(struct ab8500 *a8500, u16 addr);
+extern int ab8500_set_bits(struct ab8500 *a8500, u16 addr, u8 mask, u8 data);
+
+extern int __devinit ab8500_init(struct ab8500 *ab8500);
+extern int __devexit ab8500_exit(struct ab8500 *ab8500);
+
+#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/abx500.h
index 9a881c305a50..390726fcbcb1 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/abx500.h
@@ -3,17 +3,37 @@
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
+ *
+ * ABX500 core access functions.
+ * The abx500 interface is used for the Analog Baseband chip
+ * ab3100, ab3550, ab5500 and possibly comming. It is not used for
+ * ab4500 and ab8500 since they are another family of chip.
+ *
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/device.h>
#include <linux/regulator/machine.h>
-#ifndef MFD_AB3100_H
-#define MFD_AB3100_H
+#ifndef MFD_ABX500_H
+#define MFD_ABX500_H
-#define ABUNKNOWN 0
-#define AB3000 1
-#define AB3100 2
+#define AB3100_P1A 0xc0
+#define AB3100_P1B 0xc1
+#define AB3100_P1C 0xc2
+#define AB3100_P1D 0xc3
+#define AB3100_P1E 0xc4
+#define AB3100_P1F 0xc5
+#define AB3100_P1G 0xc6
+#define AB3100_R2A 0xc7
+#define AB3100_R2B 0xc8
+#define AB3550_P1A 0x10
+#define AB5500_1_0 0x20
+#define AB5500_2_0 0x21
+#define AB5500_2_1 0x22
/*
* AB3100, EVENTA1, A2 and A3 event register flags
@@ -89,7 +109,7 @@ struct ab3100 {
char chip_name[32];
u8 chip_id;
struct blocking_notifier_head event_subscribers;
- u32 startup_events;
+ u8 startup_events[3];
bool startup_events_read;
};
@@ -112,18 +132,102 @@ struct ab3100_platform_data {
int external_voltage;
};
-int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
-int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
-int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
- u8 first_reg, u8 *regvals, u8 numregs);
-int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
- u8 reg, u8 andmask, u8 ormask);
-u8 ab3100_get_chip_type(struct ab3100 *ab3100);
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
-int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
- u32 *fatevent);
+/* AB3550, STR register flags */
+#define AB3550_STR_ONSWA (0x01)
+#define AB3550_STR_ONSWB (0x02)
+#define AB3550_STR_ONSWC (0x04)
+#define AB3550_STR_DCIO (0x08)
+#define AB3550_STR_BOOT_MODE (0x10)
+#define AB3550_STR_SIM_OFF (0x20)
+#define AB3550_STR_BATT_REMOVAL (0x40)
+#define AB3550_STR_VBUS (0x80)
+
+/* Interrupt mask registers */
+#define AB3550_IMR1 0x29
+#define AB3550_IMR2 0x2a
+#define AB3550_IMR3 0x2b
+#define AB3550_IMR4 0x2c
+#define AB3550_IMR5 0x2d
+
+enum ab3550_devid {
+ AB3550_DEVID_ADC,
+ AB3550_DEVID_DAC,
+ AB3550_DEVID_LEDS,
+ AB3550_DEVID_POWER,
+ AB3550_DEVID_REGULATORS,
+ AB3550_DEVID_SIM,
+ AB3550_DEVID_UART,
+ AB3550_DEVID_RTC,
+ AB3550_DEVID_CHARGER,
+ AB3550_DEVID_FUELGAUGE,
+ AB3550_DEVID_VIBRATOR,
+ AB3550_DEVID_CODEC,
+ AB3550_NUM_DEVICES,
+};
+
+/**
+ * struct abx500_init_setting
+ * Initial value of the registers for driver to use during setup.
+ */
+struct abx500_init_settings {
+ u8 bank;
+ u8 reg;
+ u8 setting;
+};
+
+/**
+ * struct ab3550_platform_data
+ * Data supplied to initialize board connections to the AB3550
+ */
+struct ab3550_platform_data {
+ struct {unsigned int base; unsigned int count; } irq;
+ void *dev_data[AB3550_NUM_DEVICES];
+ size_t dev_data_sz[AB3550_NUM_DEVICES];
+ struct abx500_init_settings *init_settings;
+ unsigned int init_settings_sz;
+};
+
+int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
+ u8 value);
+int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
+ u8 *value);
+int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
+ u8 first_reg, u8 *regvals, u8 numregs);
+int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
+ u8 first_reg, u8 *regvals, u8 numregs);
+/**
+ * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
+ * target register
+ *
+ * @dev: The AB sub device.
+ * @bank: The i2c bank number.
+ * @bitmask: The bit mask to use.
+ * @bitvalues: The new bit values.
+ *
+ * Updates the value of an AB register:
+ * value -> ((value & ~bitmask) | (bitvalues & bitmask))
+ */
+int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
+ u8 reg, u8 bitmask, u8 bitvalues);
+int abx500_get_chip_id(struct device *dev);
+int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
+int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
+
+struct abx500_ops {
+ int (*get_chip_id) (struct device *);
+ int (*get_register) (struct device *, u8, u8, u8 *);
+ int (*set_register) (struct device *, u8, u8, u8);
+ int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
+ int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
+ int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
+ int (*event_registers_startup_state_get) (struct device *, u8 *);
+ int (*startup_irq_enabled) (struct device *, unsigned int);
+};
+
+int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
#endif
diff --git a/include/linux/mfd/janz.h b/include/linux/mfd/janz.h
new file mode 100644
index 000000000000..e9994c469803
--- /dev/null
+++ b/include/linux/mfd/janz.h
@@ -0,0 +1,54 @@
+/*
+ * Common Definitions for Janz MODULbus devices
+ *
+ * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef JANZ_H
+#define JANZ_H
+
+struct janz_platform_data {
+ /* MODULbus Module Number */
+ unsigned int modno;
+};
+
+/* PLX bridge chip onboard registers */
+struct janz_cmodio_onboard_regs {
+ u8 unused1;
+
+ /*
+ * Read access: interrupt status
+ * Write access: interrupt disable
+ */
+ u8 int_disable;
+ u8 unused2;
+
+ /*
+ * Read access: MODULbus number (hex switch)
+ * Write access: interrupt enable
+ */
+ u8 int_enable;
+ u8 unused3;
+
+ /* write-only */
+ u8 reset_assert;
+ u8 unused4;
+
+ /* write-only */
+ u8 reset_deassert;
+ u8 unused5;
+
+ /* read-write access to serial EEPROM */
+ u8 eep;
+ u8 unused6;
+
+ /* write-only access to EEPROM chip select */
+ u8 enid;
+};
+
+#endif /* JANZ_H */
diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h
new file mode 100644
index 000000000000..4bdf19c8eedf
--- /dev/null
+++ b/include/linux/mfd/rdc321x.h
@@ -0,0 +1,26 @@
+#ifndef __RDC321X_MFD_H
+#define __RDC321X_MFD_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+
+/* Offsets to be accessed in the southbridge PCI
+ * device configuration register */
+#define RDC321X_WDT_CTRL 0x44
+#define RDC321X_GPIO_CTRL_REG1 0x48
+#define RDC321X_GPIO_DATA_REG1 0x4c
+#define RDC321X_GPIO_CTRL_REG2 0x84
+#define RDC321X_GPIO_DATA_REG2 0x88
+
+#define RDC321X_MAX_GPIO 58
+
+struct rdc321x_gpio_pdata {
+ struct pci_dev *sb_pdev;
+ unsigned max_gpios;
+};
+
+struct rdc321x_wdt_pdata {
+ struct pci_dev *sb_pdev;
+};
+
+#endif /* __RDC321X_MFD_H */
diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h
new file mode 100644
index 000000000000..e47f770d3068
--- /dev/null
+++ b/include/linux/mfd/tc35892.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License, version 2
+ */
+
+#ifndef __LINUX_MFD_TC35892_H
+#define __LINUX_MFD_TC35892_H
+
+#include <linux/device.h>
+
+#define TC35892_RSTCTRL_IRQRST (1 << 4)
+#define TC35892_RSTCTRL_TIMRST (1 << 3)
+#define TC35892_RSTCTRL_ROTRST (1 << 2)
+#define TC35892_RSTCTRL_KBDRST (1 << 1)
+#define TC35892_RSTCTRL_GPIRST (1 << 0)
+
+#define TC35892_IRQST 0x91
+
+#define TC35892_MANFCODE_MAGIC 0x03
+#define TC35892_MANFCODE 0x80
+#define TC35892_VERSION 0x81
+#define TC35892_IOCFG 0xA7
+
+#define TC35892_CLKMODE 0x88
+#define TC35892_CLKCFG 0x89
+#define TC35892_CLKEN 0x8A
+
+#define TC35892_RSTCTRL 0x82
+#define TC35892_EXTRSTN 0x83
+#define TC35892_RSTINTCLR 0x84
+
+#define TC35892_GPIOIS0 0xC9
+#define TC35892_GPIOIS1 0xCA
+#define TC35892_GPIOIS2 0xCB
+#define TC35892_GPIOIBE0 0xCC
+#define TC35892_GPIOIBE1 0xCD
+#define TC35892_GPIOIBE2 0xCE
+#define TC35892_GPIOIEV0 0xCF
+#define TC35892_GPIOIEV1 0xD0
+#define TC35892_GPIOIEV2 0xD1
+#define TC35892_GPIOIE0 0xD2
+#define TC35892_GPIOIE1 0xD3
+#define TC35892_GPIOIE2 0xD4
+#define TC35892_GPIORIS0 0xD6
+#define TC35892_GPIORIS1 0xD7
+#define TC35892_GPIORIS2 0xD8
+#define TC35892_GPIOMIS0 0xD9
+#define TC35892_GPIOMIS1 0xDA
+#define TC35892_GPIOMIS2 0xDB
+#define TC35892_GPIOIC0 0xDC
+#define TC35892_GPIOIC1 0xDD
+#define TC35892_GPIOIC2 0xDE
+
+#define TC35892_GPIODATA0 0xC0
+#define TC35892_GPIOMASK0 0xc1
+#define TC35892_GPIODATA1 0xC2
+#define TC35892_GPIOMASK1 0xc3
+#define TC35892_GPIODATA2 0xC4
+#define TC35892_GPIOMASK2 0xC5
+
+#define TC35892_GPIODIR0 0xC6
+#define TC35892_GPIODIR1 0xC7
+#define TC35892_GPIODIR2 0xC8
+
+#define TC35892_GPIOSYNC0 0xE6
+#define TC35892_GPIOSYNC1 0xE7
+#define TC35892_GPIOSYNC2 0xE8
+
+#define TC35892_GPIOWAKE0 0xE9
+#define TC35892_GPIOWAKE1 0xEA
+#define TC35892_GPIOWAKE2 0xEB
+
+#define TC35892_GPIOODM0 0xE0
+#define TC35892_GPIOODE0 0xE1
+#define TC35892_GPIOODM1 0xE2
+#define TC35892_GPIOODE1 0xE3
+#define TC35892_GPIOODM2 0xE4
+#define TC35892_GPIOODE2 0xE5
+
+#define TC35892_INT_GPIIRQ 0
+#define TC35892_INT_TI0IRQ 1
+#define TC35892_INT_TI1IRQ 2
+#define TC35892_INT_TI2IRQ 3
+#define TC35892_INT_ROTIRQ 5
+#define TC35892_INT_KBDIRQ 6
+#define TC35892_INT_PORIRQ 7
+
+#define TC35892_NR_INTERNAL_IRQS 8
+#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
+
+struct tc35892 {
+ struct mutex lock;
+ struct device *dev;
+ struct i2c_client *i2c;
+
+ int irq_base;
+ int num_gpio;
+ struct tc35892_platform_data *pdata;
+};
+
+extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
+extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
+extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
+ u8 *values);
+extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
+ const u8 *values);
+extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
+
+/**
+ * struct tc35892_gpio_platform_data - TC35892 GPIO platform data
+ * @gpio_base: first gpio number assigned to TC35892. A maximum of
+ * %TC35892_NR_GPIOS GPIOs will be allocated.
+ */
+struct tc35892_gpio_platform_data {
+ int gpio_base;
+};
+
+/**
+ * struct tc35892_platform_data - TC35892 platform data
+ * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used.
+ * @gpio: GPIO-specific platform data
+ */
+struct tc35892_platform_data {
+ int irq_base;
+ struct tc35892_gpio_platform_data *gpio;
+};
+
+#define TC35892_NR_GPIOS 24
+#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
+
+#endif
diff --git a/include/linux/mfd/tps6507x.h b/include/linux/mfd/tps6507x.h
new file mode 100644
index 000000000000..c923e4864f55
--- /dev/null
+++ b/include/linux/mfd/tps6507x.h
@@ -0,0 +1,169 @@
+/* linux/mfd/tps6507x.h
+ *
+ * Functions to access TPS65070 power management chip.
+ *
+ * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
+ *
+ *
+ * For licencing details see kernel-base/COPYING
+ */
+
+#ifndef __LINUX_MFD_TPS6507X_H
+#define __LINUX_MFD_TPS6507X_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Registers, all 8 bits
+ * ----------------------------------------------------------------------------
+ */
+
+
+/* Register definitions */
+#define TPS6507X_REG_PPATH1 0X01
+#define TPS6507X_CHG_USB BIT(7)
+#define TPS6507X_CHG_AC BIT(6)
+#define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
+#define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
+#define TPS6507X_CHG_AC_CURRENT BIT(2)
+#define TPS6507X_CHG_USB_CURRENT BIT(0)
+
+#define TPS6507X_REG_INT 0X02
+#define TPS6507X_REG_MASK_AC_USB BIT(7)
+#define TPS6507X_REG_MASK_TSC BIT(6)
+#define TPS6507X_REG_MASK_PB_IN BIT(5)
+#define TPS6507X_REG_TSC_INT BIT(3)
+#define TPS6507X_REG_PB_IN_INT BIT(2)
+#define TPS6507X_REG_AC_USB_APPLIED BIT(1)
+#define TPS6507X_REG_AC_USB_REMOVED BIT(0)
+
+#define TPS6507X_REG_CHGCONFIG0 0X03
+
+#define TPS6507X_REG_CHGCONFIG1 0X04
+#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
+#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
+#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
+#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
+#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
+
+#define TPS6507X_REG_CHGCONFIG2 0X05
+
+#define TPS6507X_REG_CHGCONFIG3 0X06
+
+#define TPS6507X_REG_ADCONFIG 0X07
+#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7)
+#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6)
+#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5)
+#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4)
+#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0
+#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1
+#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2
+#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3
+#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4
+#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5
+#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6
+#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7
+#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8
+#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9
+#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10
+#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11
+#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12
+#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14
+#define TPS6507X_ADCONFIG_INPUT_TSC 15
+
+#define TPS6507X_REG_TSCMODE 0X08
+#define TPS6507X_TSCMODE_X_POSITION 0
+#define TPS6507X_TSCMODE_Y_POSITION 1
+#define TPS6507X_TSCMODE_PRESSURE 2
+#define TPS6507X_TSCMODE_X_PLATE 3
+#define TPS6507X_TSCMODE_Y_PLATE 4
+#define TPS6507X_TSCMODE_STANDBY 5
+#define TPS6507X_TSCMODE_ADC_INPUT 6
+#define TPS6507X_TSCMODE_DISABLE 7
+
+#define TPS6507X_REG_ADRESULT_1 0X09
+
+#define TPS6507X_REG_ADRESULT_2 0X0A
+#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0))
+
+#define TPS6507X_REG_PGOOD 0X0B
+
+#define TPS6507X_REG_PGOODMASK 0X0C
+
+#define TPS6507X_REG_CON_CTRL1 0X0D
+#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
+#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
+#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
+#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
+#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
+
+#define TPS6507X_REG_CON_CTRL2 0X0E
+
+#define TPS6507X_REG_CON_CTRL3 0X0F
+
+#define TPS6507X_REG_DEFDCDC1 0X10
+#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7)
+#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F
+
+#define TPS6507X_REG_DEFDCDC2_LOW 0X11
+#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F
+
+#define TPS6507X_REG_DEFDCDC2_HIGH 0X12
+#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F
+
+#define TPS6507X_REG_DEFDCDC3_LOW 0X13
+#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F
+
+#define TPS6507X_REG_DEFDCDC3_HIGH 0X14
+#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F
+
+#define TPS6507X_REG_DEFSLEW 0X15
+
+#define TPS6507X_REG_LDO_CTRL1 0X16
+#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F
+
+#define TPS6507X_REG_DEFLDO2 0X17
+#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F
+
+#define TPS6507X_REG_WLED_CTRL1 0X18
+
+#define TPS6507X_REG_WLED_CTRL2 0X19
+
+/* VDCDC MASK */
+#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F
+
+#define TPS6507X_MAX_REGISTER 0X19
+
+/**
+ * struct tps6507x_board - packages regulator and touchscreen init data
+ * @tps6507x_regulator_data: regulator initialization values
+ *
+ * Board data may be used to initialize regulator and touchscreen.
+ */
+
+struct tps6507x_board {
+ struct regulator_init_data *tps6507x_pmic_init_data;
+ struct touchscreen_init_data *tps6507x_ts_init_data;
+};
+
+/**
+ * struct tps6507x_dev - tps6507x sub-driver chip access routines
+ * @read_dev() - I2C register read function
+ * @write_dev() - I2C register write function
+ *
+ * Device data may be used to access the TPS6507x chip
+ */
+
+struct tps6507x_dev {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
+ void *dest);
+ int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
+ void *src);
+
+ /* Client devices */
+ struct tps6507x_pmic *pmic;
+ struct tps6507x_ts *ts;
+};
+
+#endif /* __LINUX_MFD_TPS6507X_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 5915f6e3d9ab..eb5bd4e0e03c 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -256,8 +256,9 @@ struct wm831x {
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
/* Chip revision based flags */
- unsigned has_gpio_ena:1; /* Has GPIO enable bit */
- unsigned has_cs_sts:1; /* Has current sink status bit */
+ unsigned has_gpio_ena:1; /* Has GPIO enable bit */
+ unsigned has_cs_sts:1; /* Has current sink status bit */
+ unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
int num_gpio;