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| author | Mika Kahola <mika.kahola@intel.com> | 2026-01-19 12:37:54 +0300 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2026-01-20 11:53:01 +0300 |
| commit | 4fa244583e77fba2388f05a44f400f44f79da396 (patch) | |
| tree | dd1190c8e7813f6341fca1e98c34a4450205b7df /include/linux/zstd_errors.h | |
| parent | 10d187b3560a45e6cf829a9c52ee54c6dfb42f3a (diff) | |
| download | linux-4fa244583e77fba2388f05a44f400f44f79da396.tar.xz | |
drm/i915/cx0: Drop C20 25.175 MHz rate
Drop C20 25.175 MHz PLL table as with these
PLL dividers the port clock will be incorrectly
calculated to 25.2 MHz. For 25.175 MHz rate the
PLl dividers are calculated algorithmically making
PLL table for this rate redundant.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-14-mika.kahola@intel.com
Diffstat (limited to 'include/linux/zstd_errors.h')
0 files changed, 0 insertions, 0 deletions