diff options
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2017-05-30 17:31:21 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-06-06 22:01:15 +0300 |
| commit | fc0b2acc754a183aa79e2abb8bca8fd915832694 (patch) | |
| tree | 9c9292e44d473ed9168d0d4b023b4fbcd08bc4bd /include/linux/pxa2xx_ssp.h | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff) | |
| download | linux-fc0b2acc754a183aa79e2abb8bca8fd915832694.tar.xz | |
spi: pxa2xx: Add support for Intel Cannonlake
Intel Cannonlake LPSS SPI has up to four chip selects per port like in
Broxton and is clocked like Sunrisepoint and Kaby Lake. Add a new type
LPSS_CNL_SSP and configuration that enable runtime chip select detection
and use the same FIFO thresholds than in Sunrisepoint.
Patch adds support for both Cannonlake SoC and PCH.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/pxa2xx_ssp.h')
| -rw-r--r-- | include/linux/pxa2xx_ssp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index a0522328d7aa..8461b18e4608 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -196,6 +196,7 @@ enum pxa_ssp_type { LPSS_BSW_SSP, LPSS_SPT_SSP, LPSS_BXT_SSP, + LPSS_CNL_SSP, }; struct ssp_device { |