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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-10-14 04:23:55 +0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-10-14 04:23:55 +0400 |
| commit | f1bfbd984b4e2177886507b6a0ec5faeb6d7c217 (patch) | |
| tree | ead8f9a3d466824960f6bd6f70a8b572fa60f16d /include/linux/pci_ids.h | |
| parent | df133e8fa8e1d4afa57c84953bf80eaed2b145e0 (diff) | |
| parent | aece118e487a744eafcdd0c77fe32b55ee2092a1 (diff) | |
| download | linux-f1bfbd984b4e2177886507b6a0ec5faeb6d7c217.tar.xz | |
Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar:
"The main changes in this tree are:
- fix and update Intel Quark [Galileo] SoC platform support
- update IOSF chipset side band interface and make it available via
debugfs
- enable HPETs on Soekris net6501 and other e6xx based systems"
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache()
x86: Quark: Comment setup_arch() to document TLB/PGE bug
x86/intel/quark: Switch off CR4.PGE so TLB flush uses CR3 instead
x86/platform/intel/iosf: Add debugfs config option for IOSF
x86/platform/intel/iosf: Add better description of IOSF driver in config
x86/platform/intel/iosf: Add Braswell PCI ID
x86/platform/pmc_atom: Fix warning when CONFIG_DEBUG_FS=n
x86: HPET force enable for e6xx based systems
x86/iosf: Add debugfs support
x86/iosf: Add Kconfig prompt for IOSF_MBI selection
Diffstat (limited to 'include/linux/pci_ids.h')
| -rw-r--r-- | include/linux/pci_ids.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 0aa51b451597..24f97bf74266 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2878,6 +2878,7 @@ #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 #define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a +#define PCI_DEVICE_ID_INTEL_E6XX_CU 0x8183 #define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 |