diff options
| author | Bean Huo (beanhuo) <beanhuo@micron.com> | 2017-12-04 15:34:47 +0300 |
|---|---|---|
| committer | Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-12-13 02:36:00 +0300 |
| commit | 20ccb993f29bd6ad17699dd0b349db086e3ca719 (patch) | |
| tree | 973615108d678dc46e483299d4ed856dc925c145 /include/linux/mtd | |
| parent | 6d17969c8eb454116d906005a6c4752f4f560b26 (diff) | |
| download | linux-20ccb993f29bd6ad17699dd0b349db086e3ca719.tar.xz | |
mtd: spi-nor: check FSR error bits for Micron memories
For Micron spi nor device, when erase/program operation
fails, especially the failure results from intending to
modify protected space, spi-nor upper layers still get
the return which shows the operation succeeds. This is
because current spi_nor_fsr_ready() only uses FSR bit.7
(flag status register) to check device whether ready.
This patch fixes this issue by checking relevant error
bits in FSR.
The FSR is a powerful tool to investigate the status of
device, checking information regarding what the memory is
actually doing and detecting possible error conditions.
Signed-off-by: beanhuo <beanhuo@micron.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d0c66a0975cf..c0836cca5280 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -61,6 +61,7 @@ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ +#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ @@ -130,7 +131,10 @@ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ /* Flag Status Register bits */ -#define FSR_READY BIT(7) +#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ +#define FSR_E_ERR BIT(5) /* Erase operation status */ +#define FSR_P_ERR BIT(4) /* Program operation status */ +#define FSR_PT_ERR BIT(1) /* Protection error bit */ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ |