diff options
| author | Marc Zyngier <maz@kernel.org> | 2019-07-25 17:30:51 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2019-08-20 12:23:35 +0300 |
| commit | ad5a78d3da81836c88d1f2d53310484462660997 (patch) | |
| tree | 669099a397f32c0356df947805229ba68e0b4579 /include/linux/irqchip | |
| parent | 5f51f803826e4f4aedff415ddaf14efa707be5a7 (diff) | |
| download | linux-ad5a78d3da81836c88d1f2d53310484462660997.tar.xz | |
irqchip/gic-v3: Warn about inconsistent implementations of extended ranges
As is it usual for the GIC, it isn't disallowed to put together a system
that is majorly inconsistent, with a distributor supporting the
extended ranges while some of the CPUs don't.
Kindly tell the user that things are sailing isn't going to be smooth.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9ec3349dee04..5cc10cf7cb3e 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -496,6 +496,7 @@ #define ICC_CTLR_EL1_A3V_SHIFT 15 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) #define ICC_CTLR_EL1_RSS (0x1 << 18) +#define ICC_CTLR_EL1_ExtRange (0x1 << 19) #define ICC_PMR_EL1_SHIFT 0 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) #define ICC_BPR0_EL1_SHIFT 0 |