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| author | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 19:42:57 +0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 19:42:57 +0400 |
| commit | e36087998a3b01f3c6c93fa9465e40103f427315 (patch) | |
| tree | 029c1db87eb84dc72e796174455f0c453885fa74 /include/linux/in6.h | |
| parent | 3b8f5030ddcf51112542e1e6ef27da237642069d (diff) | |
| parent | 8097171e19bb69f3e2226827440b71ececa5d74f (diff) | |
| download | linux-e36087998a3b01f3c6c93fa9465e40103f427315.tar.xz | |
Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc
Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:
- PM support
- Fix L2 useless setting
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Remove useless L2C AUX setting
ARM: zynq: Rename 'zynq_platform_cpu_die'
ARM: zynq: Remove hotplug.c
ARM: zynq: Synchronise zynq_cpu_die/kill
ARM: zynq: cpuidle: Remove pointless code
ARM: zynq: Remove invalidate cache for cpu die
ARM: zynq: PM: Enable DDR clock stop
ARM: zynq: DT: Add DDRC node
Documentation: devicetree: Add binding for Synopsys DDR controller
ARM: zynq: PM: Enable A9 internal clock gating feature
Diffstat (limited to 'include/linux/in6.h')
0 files changed, 0 insertions, 0 deletions