diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-03-15 18:42:05 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-03-20 16:26:03 +0300 |
| commit | 59af78d78db8bde6a63e09772aa44192f772fa96 (patch) | |
| tree | a655fc75c28c5204c6403a4653c9be8b10e5ae0d /include/linux/clk | |
| parent | 68d724cedcca8ab86eee824682f7da0af5e6e50d (diff) | |
| download | linux-59af78d78db8bde6a63e09772aa44192f772fa96.tar.xz | |
clk: tegra: Add SATA seq input control
This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/linux/clk')
| -rw-r--r-- | include/linux/clk/tegra.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index e17d32831e28..d23c9cf26993 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -125,6 +125,7 @@ extern void tegra210_xusb_pll_hw_control_enable(void); extern void tegra210_xusb_pll_hw_sequence_start(void); extern void tegra210_sata_pll_hw_control_enable(void); extern void tegra210_sata_pll_hw_sequence_start(void); +extern void tegra210_set_sata_pll_seq_sw(bool state); extern void tegra210_put_utmipll_in_iddq(void); extern void tegra210_put_utmipll_out_iddq(void); |