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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2014-09-15 20:15:53 +0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-09-22 13:38:59 +0400
commitbcc5fd49a0fda5abc22057f65b318788ccb5d2ad (patch)
treeedf97c273ea66306e5a6fdd81e6c5a78d31e8873 /include/linux/clk
parent5db722eeba0051c68e638114f6720e715b03cd2c (diff)
downloadlinux-bcc5fd49a0fda5abc22057f65b318788ccb5d2ad.tar.xz
clk: at91: add a driver for the h32mx clock
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/at91_pmc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index de4268d4987a..c8e3b3d1eded 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -125,6 +125,7 @@ extern void __iomem *at91_pmc_base;
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
+#define AT91_PMC_H32MXDIV BIT(24)
#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */