diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-01-15 22:47:22 +0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-01-17 00:00:57 +0400 |
| commit | 3fa2252b7a78a8057017471a28f47b306e95ee26 (patch) | |
| tree | e3cf04e4099a9414b15d27f6428f7726f29d7a05 /include/linux/clk-provider.h | |
| parent | d0d44dd4ac58bc547646a9d0e65b4648f97cb533 (diff) | |
| download | linux-3fa2252b7a78a8057017471a28f47b306e95ee26.tar.xz | |
clk: Add set_rate_and_parent() op
Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/linux/clk-provider.h')
| -rw-r--r-- | include/linux/clk-provider.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 5429f5db5037..999b28ba38f7 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -116,6 +116,18 @@ struct clk_hw; * set then clock accuracy will be initialized to parent accuracy * or 0 (perfect clock) if clock has no parent. * + * @set_rate_and_parent: Change the rate and the parent of this clock. The + * requested rate is specified by the second argument, which + * should typically be the return of .round_rate call. The + * third argument gives the parent rate which is likely helpful + * for most .set_rate_and_parent implementation. The fourth + * argument gives the parent index. This callback is optional (and + * unnecessary) for clocks with 0 or 1 parents as well as + * for clocks that can tolerate switching the rate and the parent + * separately via calls to .set_parent and .set_rate. + * Returns 0 on success, -EERROR otherwise. + * + * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts. If enabling a clock requires code that might sleep, @@ -147,6 +159,9 @@ struct clk_ops { u8 (*get_parent)(struct clk_hw *hw); int (*set_rate)(struct clk_hw *hw, unsigned long, unsigned long); + int (*set_rate_and_parent)(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, u8 index); unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); void (*init)(struct clk_hw *hw); |