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authorShaohua Li <shaohua.li@intel.com>2009-10-29 06:04:50 +0300
committerLen Brown <len.brown@intel.com>2009-12-16 22:05:11 +0300
commit3a9622dc4659af44a8098a233f65c51e495ff0a5 (patch)
tree8e0dd5d1f31ad6a9047b0ba5faf26a3759d9e2fd /include/linux/acpi.h
parent70023de88c58a81a730ab4d13c51a30e537ec76e (diff)
downloadlinux-3a9622dc4659af44a8098a233f65c51e495ff0a5.tar.xz
ACPI: cleanup pci_root _OSC code.
Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'include/linux/acpi.h')
-rw-r--r--include/linux/acpi.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 3247e09db20d..535beecc37cf 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -263,7 +263,6 @@ struct acpi_osc_context {
#define OSC_QUERY_TYPE 0
#define OSC_SUPPORT_TYPE 1
#define OSC_CONTROL_TYPE 2
-#define OSC_SUPPORT_MASKS 0x1f
/* _OSC DW0 Definition */
#define OSC_QUERY_ENABLE 1
@@ -274,12 +273,14 @@ struct acpi_osc_context {
acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
+/* PCI defined _OSC bits */
/* _OSC DW1 Definition (OS Support Fields) */
#define OSC_EXT_PCI_CONFIG_SUPPORT 1
#define OSC_ACTIVE_STATE_PWR_SUPPORT 2
#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4
#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8
#define OSC_MSI_SUPPORT 16
+#define OSC_PCI_SUPPORT_MASKS 0x1f
/* _OSC DW1 Definition (OS Control Fields) */
#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1
@@ -288,7 +289,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
#define OSC_PCI_EXPRESS_AER_CONTROL 8
#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16
-#define OSC_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \
+#define OSC_PCI_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \
OSC_SHPC_NATIVE_HP_CONTROL | \
OSC_PCI_EXPRESS_PME_CONTROL | \
OSC_PCI_EXPRESS_AER_CONTROL | \