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| author | Stephen Boyd <sboyd@kernel.org> | 2020-06-23 22:12:43 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-06-23 22:12:43 +0300 |
| commit | 7aae3c161e0677018d6b3be2b79c4dbbedda9091 (patch) | |
| tree | 745675d5eaa699b998063f810a6f1f587aed33d2 /include/dt-bindings | |
| parent | ef01ab612b527eb8cdec0a5d3c06849ca92bcf90 (diff) | |
| parent | 260249f929e81d3d5764117fdd6b9e43eb8fb1d5 (diff) | |
| download | linux-7aae3c161e0677018d6b3be2b79c4dbbedda9091.tar.xz | |
Merge branch 'clk-vc5' into clk-next
* clk-vc5:
clk: vc5: Enable addition output configurations of the Versaclock
dt: Add additional option bindings for IDT VersaClock
clk: vc5: Allow Versaclock driver to support multiple instances
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clk/versaclock.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h new file mode 100644 index 000000000000..c6a6a0946564 --- /dev/null +++ b/include/dt-bindings/clk/versaclock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* This file defines field values used by the versaclock 6 family + * for defining output type + */ + +#define VC5_LVPECL 0 +#define VC5_CMOS 1 +#define VC5_HCSL33 2 +#define VC5_LVDS 3 +#define VC5_CMOS2 4 +#define VC5_CMOSD 5 +#define VC5_HCSL25 6 |