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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-03-04 20:36:29 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-03-04 20:36:29 +0300 |
| commit | 37655fae0c579315624189a7708d0b688d473876 (patch) | |
| tree | b171c2ea6ea1434893cbd0c4de5608486d9b1cc8 /include/dt-bindings | |
| parent | 8626556f259331aac23c0e274aed24420f0e5403 (diff) | |
| parent | 7af8a26ce7055dd74853ea7c2b9752961e3491da (diff) | |
| download | linux-37655fae0c579315624189a7708d0b688d473876.tar.xz | |
Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull second batch of rockchip clk updates from Heiko Stuebner:
Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.
* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: include downstream muxes into fractional dividers on rk3368
clk: rockchip: set the clock ids for RK3228 HDMI
clk: rockchip: set the clock ids for RK3228 VOP
clk: rockchip: add the tsadc clocks found on rk3228 SoCs
clk: rockchip: add the new clock ids for RK3228 HDMI
clk: rockchip: add the new clock ids for RK3228 VOP
clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
clk: rockchip: fix coding style for clk-cpu.c
clk: rockchip: don't return NULL when registering mmc branch fails
clk: rockchip: don't return NULL when registering inverter fails
clk: rockchip: check grf when waiting pll lock
clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index a78dd891e24a..5d43ed9b05ad 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -29,6 +29,7 @@ #define SCLK_SDMMC 68 #define SCLK_SDIO 69 #define SCLK_EMMC 71 +#define SCLK_TSADC 72 #define SCLK_UART0 77 #define SCLK_UART1 78 #define SCLK_UART2 79 @@ -49,10 +50,17 @@ #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 /* aclk gates */ #define ACLK_DMAC 194 #define ACLK_PERI 210 +#define ACLK_VOP 211 /* pclk gates */ #define PCLK_GPIO0 320 @@ -68,11 +76,15 @@ #define PCLK_UART0 341 #define PCLK_UART1 342 #define PCLK_UART2 343 +#define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 #define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 /* hclk gates */ +#define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 |