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authorStephen Boyd <sboyd@codeaurora.org>2016-02-26 02:18:12 +0300
committerStephen Boyd <sboyd@codeaurora.org>2016-02-26 02:18:12 +0300
commit7450ca6c324bf817eedfa73250e77de109bd700c (patch)
treee1e064e4778c8e7195914a328bbf884beae96e29 /include/dt-bindings
parent1594d568c6e32f10b00ac2a23c6d506a66a09607 (diff)
parenta6cb74cbc927af04af827ef590082f9717ffad51 (diff)
downloadlinux-7450ca6c324bf817eedfa73250e77de109bd700c.tar.xz
Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver changes from Sylwester Nawrocki: Mostly correction of errors in the exynos5433 SoC clocks definition, dropping read-only registers from the suspend/resume register save/restore list and exposition of two clocks required for the exynos5433 HDMI subsystem operation. * tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung: clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition clk: samsung: exynos5433: Drop RO registers from the save/restore lists clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names clk/samsung: exynos5433: add pclk_decon clock clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5433.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 5bd80d5ecd0f..8e024fea26e7 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,12 @@
#define CLK_SCLK_RGB_VCLK 109
#define CLK_SCLK_RGB_TV_VCLK 110
-#define DISP_NR_CLK 111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112
+
+#define CLK_PCLK_DECON 113
+
+#define DISP_NR_CLK 114
/* CMU_AUD */
#define CLK_MOUT_AUD_PLL_USER 1
@@ -1298,7 +1303,7 @@
#define CLK_MOUT_ACLK_LITE_C_B 13
#define CLK_MOUT_ACLK_LITE_C_A 14
-#define CLK_DIV_SCLK_ISP_WPWM 15
+#define CLK_DIV_SCLK_ISP_MPWM 15
#define CLK_DIV_PCLK_CAM1_83 16
#define CLK_DIV_PCLK_CAM1_166 17
#define CLK_DIV_PCLK_DBG_CAM1 18