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authorEnric Balletbo i Serra <enric.balletbo@collabora.com>2018-05-09 15:57:44 +0300
committerMyungJoo Ham <myungjoo.ham@samsung.com>2018-07-18 07:58:30 +0300
commit49502b23e0e45b57b776490cfdfd95ea7fecd7c7 (patch)
tree27044eec71fbc4c55ed7f91b2d334f6667ff169d /include/dt-bindings
parent2d2894c94a61930615cd1411cd8e0bf5b804e3a1 (diff)
downloadlinux-49502b23e0e45b57b776490cfdfd95ea7fecd7c7.tar.xz
dt-bindings: clock: add rk3399 DDR3 standard speed bins.
DDR3 SDRAM Standard (JESD79-3F) defines some standard speed bins for DDR3 memories. The rk3399_dmc driver allows you to pass these values via the device tree. For that purpose the devfreq/rk3399_dmc.txt binding refers to a ddr.h file which does not exist. This patch adds the missing defines in a include file called rk3399-ddr.h with the definition of standard speed bins according to the ARM Trusted Firmware (ATF). Fixes: c1ceb8f7c167 (Documentation: bindings: add dt documentation for rk3399 dmc) Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/rk3399-ddr.h56
1 files changed, 56 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3399-ddr.h b/include/dt-bindings/clock/rk3399-ddr.h
new file mode 100644
index 000000000000..ed2280844963
--- /dev/null
+++ b/include/dt-bindings/clock/rk3399-ddr.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef DT_BINDINGS_DDR_H
+#define DT_BINDINGS_DDR_H
+
+/*
+ * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
+ * each corresponding bin.
+ */
+
+/* DDR3-800 (5-5-5) */
+#define DDR3_800D 0
+/* DDR3-800 (6-6-6) */
+#define DDR3_800E 1
+/* DDR3-1066 (6-6-6) */
+#define DDR3_1066E 2
+/* DDR3-1066 (7-7-7) */
+#define DDR3_1066F 3
+/* DDR3-1066 (8-8-8) */
+#define DDR3_1066G 4
+/* DDR3-1333 (7-7-7) */
+#define DDR3_1333F 5
+/* DDR3-1333 (8-8-8) */
+#define DDR3_1333G 6
+/* DDR3-1333 (9-9-9) */
+#define DDR3_1333H 7
+/* DDR3-1333 (10-10-10) */
+#define DDR3_1333J 8
+/* DDR3-1600 (8-8-8) */
+#define DDR3_1600G 9
+/* DDR3-1600 (9-9-9) */
+#define DDR3_1600H 10
+/* DDR3-1600 (10-10-10) */
+#define DDR3_1600J 11
+/* DDR3-1600 (11-11-11) */
+#define DDR3_1600K 12
+/* DDR3-1600 (10-10-10) */
+#define DDR3_1866J 13
+/* DDR3-1866 (11-11-11) */
+#define DDR3_1866K 14
+/* DDR3-1866 (12-12-12) */
+#define DDR3_1866L 15
+/* DDR3-1866 (13-13-13) */
+#define DDR3_1866M 16
+/* DDR3-2133 (11-11-11) */
+#define DDR3_2133K 17
+/* DDR3-2133 (12-12-12) */
+#define DDR3_2133L 18
+/* DDR3-2133 (13-13-13) */
+#define DDR3_2133M 19
+/* DDR3-2133 (14-14-14) */
+#define DDR3_2133N 20
+/* DDR3 ATF default */
+#define DDR3_DEFAULT 21
+
+#endif