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| author | Arnd Bergmann <arnd@arndb.de> | 2017-08-16 22:55:03 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-08-16 22:55:03 +0300 |
| commit | f822e600854cfd3fa965aa3acfd162e8631161fd (patch) | |
| tree | a7eb965605526c6d9757bd8f59a6078e644b4dfd /include/dt-bindings | |
| parent | 900452f3046521845fb7c3b1e263e8c9cd4c4827 (diff) | |
| parent | 105ae504a3eb6c2e188e8d67db59b71186f11967 (diff) | |
| download | linux-f822e600854cfd3fa965aa3acfd162e8631161fd.tar.xz | |
Merge tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Pull "Renesas ARM Based SoC Drivers Updates for v4.14" from Simon Horman:
Add R-Car D3 (r8a77995) support to the Renesas-specific SoC drivers
- SoC identification
- System controller
- Reset controller
* tag 'renesas-drivers-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
soc: renesas: rcar-rst: Add support for R-Car D3
soc: renesas: rcar-sysc: Add support for R-Car D3 power areas
soc: renesas: Add r8a77995 SYSC PM Domain Binding Definitions
soc: renesas: Identify R-Car D3
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/power/r8a77995-sysc.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h new file mode 100644 index 000000000000..09d0ed575b73 --- /dev/null +++ b/include/dt-bindings/power/r8a77995-sysc.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77995_PD_CA53_CPU0 5 +#define R8A77995_PD_CA53_SCU 21 + +/* Always-on power area */ +#define R8A77995_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */ |