diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-08-05 13:27:13 +0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-08-05 13:27:13 +0400 |
| commit | 7109561524dc57b95fd3f9b61547268b9b6db8ed (patch) | |
| tree | df08f565b2c616b7e68fe35cd428a8c5ba3bfcb1 /include/dt-bindings | |
| parent | 6bf755db4d5e7ccea61fb17727a183b9bd8945b1 (diff) | |
| parent | 3bb70de692f70861f5c5729cd2b870d0104a7cc9 (diff) | |
| download | linux-7109561524dc57b95fd3f9b61547268b9b6db8ed.tar.xz | |
Merge branches 'fixes' and 'misc' into for-next
Conflicts:
arch/arm/kernel/iwmmxt.S
arch/arm/mm/cache-l2x0.c
arch/arm/mm/mmu.c
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/stih415-clks.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/stih416-clks.h | 1 |
3 files changed, 4 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index 7cf5c9969336..b91dd462ba85 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -145,6 +145,7 @@ #define IMX6SL_CLK_USDHC4 132 #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 #define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_END 135 +#define IMX6SL_CLK_ENET 135 +#define IMX6SL_CLK_END 136 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/stih415-clks.h b/include/dt-bindings/clock/stih415-clks.h index 0d2c7397e028..d80caa68aebd 100644 --- a/include/dt-bindings/clock/stih415-clks.h +++ b/include/dt-bindings/clock/stih415-clks.h @@ -10,6 +10,7 @@ #define CLK_ETH1_PHY 4 /* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 #define CLK_GMAC0_PHY 3 #endif diff --git a/include/dt-bindings/clock/stih416-clks.h b/include/dt-bindings/clock/stih416-clks.h index 552c779eb6af..f9bdbd13568d 100644 --- a/include/dt-bindings/clock/stih416-clks.h +++ b/include/dt-bindings/clock/stih416-clks.h @@ -10,6 +10,7 @@ #define CLK_ETH1_PHY 4 /* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 #define CLK_GMAC0_PHY 3 #endif |