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authorJon Hunter <jonathanh@nvidia.com>2022-10-03 15:51:41 +0300
committerThierry Reding <treding@nvidia.com>2022-11-21 15:27:17 +0300
commit41155b6f6db8742c5f5247a141eca89c601c258c (patch)
treeba57ad296ac04db597365b24811c696bc392d134 /include/dt-bindings/power
parent0e2b014eeb257173c72014ebd02ab0d60643f0f8 (diff)
downloadlinux-41155b6f6db8742c5f5247a141eca89c601c258c.tar.xz
dt-bindings: tegra: Update headers for Tegra234
Update the device-tree clock, memory, power and reset headers for Tegra234 by adding the definitions for all the various devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/power')
-rw-r--r--include/dt-bindings/power/tegra234-powergate.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
index 73b1321fedf8..b0fec2ddec84 100644
--- a/include/dt-bindings/power/tegra234-powergate.h
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -4,6 +4,7 @@
#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
#define __ABI_MACH_T234_POWERGATE_T234_H_
+#define TEGRA234_POWER_DOMAIN_OFA 1U
#define TEGRA234_POWER_DOMAIN_AUD 2U
#define TEGRA234_POWER_DOMAIN_DISP 3U
#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U
@@ -11,6 +12,9 @@
#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U
#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U
#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U
+#define TEGRA234_POWER_DOMAIN_XUSBA 10U
+#define TEGRA234_POWER_DOMAIN_XUSBB 11U
+#define TEGRA234_POWER_DOMAIN_XUSBC 12U
#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U
#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U
#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U
@@ -19,7 +23,17 @@
#define TEGRA234_POWER_DOMAIN_MGBEB 18U
#define TEGRA234_POWER_DOMAIN_MGBEC 19U
#define TEGRA234_POWER_DOMAIN_MGBED 20U
+#define TEGRA234_POWER_DOMAIN_ISPA 22U
#define TEGRA234_POWER_DOMAIN_NVDEC 23U
+#define TEGRA234_POWER_DOMAIN_NVJPGA 24U
+#define TEGRA234_POWER_DOMAIN_NVENC 25U
+#define TEGRA234_POWER_DOMAIN_VI 28U
#define TEGRA234_POWER_DOMAIN_VIC 29U
+#define TEGRA234_POWER_DOMAIN_PVA 30U
+#define TEGRA234_POWER_DOMAIN_DLAA 32U
+#define TEGRA234_POWER_DOMAIN_DLAB 33U
+#define TEGRA234_POWER_DOMAIN_CV 34U
+#define TEGRA234_POWER_DOMAIN_GPU 35U
+#define TEGRA234_POWER_DOMAIN_NVJPGB 36U
#endif