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| author | Steve French <sfrench@us.ibm.com> | 2007-07-19 04:38:57 +0400 |
|---|---|---|
| committer | Steve French <sfrench@us.ibm.com> | 2007-07-19 04:38:57 +0400 |
| commit | 1ff8392c32a2645d2665ca779ecb91bb29361c13 (patch) | |
| tree | 860b95e9a499ade4060848740fc6ce1fbb4e4e8d /include/asm-sh/cpu-sh2/cache.h | |
| parent | 70b315b0dd3879cb3ab8aadffb14f10b2d19b9c3 (diff) | |
| parent | 5bae7ac9feba925fd0099057f6b23d7be80b7b41 (diff) | |
| download | linux-1ff8392c32a2645d2665ca779ecb91bb29361c13.tar.xz | |
Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
fs/cifs/export.c
Diffstat (limited to 'include/asm-sh/cpu-sh2/cache.h')
| -rw-r--r-- | include/asm-sh/cpu-sh2/cache.h | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h index 20b9796842dc..f02ba7a672b2 100644 --- a/include/asm-sh/cpu-sh2/cache.h +++ b/include/asm-sh/cpu-sh2/cache.h @@ -12,23 +12,7 @@ #define L1_CACHE_SHIFT 4 -#if defined(CONFIG_CPU_SUBTYPE_SH7604) -#define CCR 0xfffffe92 /* Address of Cache Control Register */ - -#define CCR_CACHE_CE 0x01 /* Cache enable */ -#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */ -#define CCR_CACHE_OD 0x04 /* Data Replacement disable */ -#define CCR_CACHE_TW 0x08 /* Two-way mode */ -#define CCR_CACHE_CP 0x10 /* Cache purge */ - -#define CACHE_OC_ADDRESS_ARRAY 0x60000000 - -#define CCR_CACHE_ENABLE CCR_CACHE_CE -#define CCR_CACHE_INVALIDATE CCR_CACHE_CP -#define CCR_CACHE_ORA CCR_CACHE_TW -#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ - -#elif defined(CONFIG_CPU_SUBTYPE_SH7619) +#if defined(CONFIG_CPU_SUBTYPE_SH7619) #define CCR1 0xffffffec #define CCR CCR1 @@ -49,5 +33,5 @@ #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF #endif -#endif /* __ASM_CPU_SH2_CACHE_H */ +#endif /* __ASM_CPU_SH2_CACHE_H */ |