diff options
| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2006-03-13 12:23:03 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-18 19:59:27 +0300 |
| commit | de62893bc0725f8b5f0445250577cd7a10b2d8f8 (patch) | |
| tree | 3a5d77b8e8aa66113431ebe287c552749c2e8fee /include/asm-mips | |
| parent | a3c4946db4fe64cb21b66a09e89890678aac6d65 (diff) | |
| download | linux-de62893bc0725f8b5f0445250577cd7a10b2d8f8.tar.xz | |
[MIPS] local_r4k_flush_cache_page fix
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly. Make
blast_?cache_page_indexed() masks its index value correctly. Also,
use physical address for physically indexed pcache/scache.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 3 | ||||
| -rw-r--r-- | include/asm-mips/cpu-info.h | 1 | ||||
| -rw-r--r-- | include/asm-mips/r4kcache.h | 3 |
3 files changed, 6 insertions, 1 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 78c9cc2735d5..3f2b6d9ac45e 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -96,6 +96,9 @@ #ifndef cpu_has_ic_fills_f_dc #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) #endif +#ifndef cpu_has_pindexed_dcache +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#endif /* * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h index d5cf519f8fcc..140be1c67da7 100644 --- a/include/asm-mips/cpu-info.h +++ b/include/asm-mips/cpu-info.h @@ -39,6 +39,7 @@ struct cache_desc { #define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ #define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ #define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ +#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ struct cpuinfo_mips { unsigned long udelay_val; diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 9632c27dad15..0bcb79a58ee9 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \ \ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ { \ - unsigned long start = page; \ + unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ + unsigned long start = INDEX_BASE + (page & indexmask); \ unsigned long end = start + PAGE_SIZE; \ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ unsigned long ws_end = current_cpu_data.desc.ways << \ |