diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-06-15 17:00:12 +0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 22:31:23 +0400 |
| commit | 02416dcf5a94af34bcd28b4baf25bbbf399d8136 (patch) | |
| tree | 1906c4266d4e28ef0b13d0579a145603dcbcff1b /include/asm-mips/cpu-features.h | |
| parent | aac8aa7717a23a9bf8740dbfb59755b1d62f04bf (diff) | |
| download | linux-02416dcf5a94af34bcd28b4baf25bbbf399d8136.tar.xz | |
Redo RM9000 workaround which along with other DSP ASE changes was
causing some headache for debuggers knowing about signal frames.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-features.h')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 4930824a43aa..bb2212cf460a 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -109,17 +109,6 @@ #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) #endif -/* - * Certain CPUs may throw bizarre exceptions if not the whole cacheline - * contains valid instructions. For these we ensure proper alignment of - * signal trampolines and pad them to the size of a full cache lines with - * nops. This is also used in structure definitions so can't be a test macro - * like the others. - */ -#ifndef PLAT_TRAMPOLINE_STUFF_LINE -#define PLAT_TRAMPOLINE_STUFF_LINE 0UL -#endif - #ifdef CONFIG_32BIT # ifndef cpu_has_nofpuex # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) |