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| author | David Woodhouse <dwmw2@infradead.org> | 2007-10-13 17:58:23 +0400 |
|---|---|---|
| committer | David Woodhouse <dwmw2@infradead.org> | 2007-10-13 17:58:23 +0400 |
| commit | ebf8889bd1fe3615991ff4494635d237280652a2 (patch) | |
| tree | 10fb735717122bbb86474339eac07f26e7ccdf40 /include/asm-blackfin/mach-bf533/mem_map.h | |
| parent | b160292cc216a50fd0cd386b0bda2cd48352c73b (diff) | |
| parent | 752097cec53eea111d087c545179b421e2bde98a (diff) | |
| download | linux-ebf8889bd1fe3615991ff4494635d237280652a2.tar.xz | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-blackfin/mach-bf533/mem_map.h')
| -rw-r--r-- | include/asm-blackfin/mach-bf533/mem_map.h | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h index e84baa3e939d..94d8c4062eb7 100644 --- a/include/asm-blackfin/mach-bf533/mem_map.h +++ b/include/asm-blackfin/mach-bf533/mem_map.h @@ -51,10 +51,10 @@ /* Level 1 Memory */ -#ifdef CONFIG_BLKFIN_CACHE -#define BLKFIN_ICACHESIZE (16*1024) +#ifdef CONFIG_BFIN_ICACHE +#define BFIN_ICACHESIZE (16*1024) #else -#define BLKFIN_ICACHESIZE (0*1024) +#define BFIN_ICACHESIZE (0*1024) #endif /* Memory Map for ADSP-BF533 processors */ @@ -64,35 +64,35 @@ #define L1_DATA_A_START 0xFF800000 #define L1_DATA_B_START 0xFF900000 -#ifdef CONFIG_BLKFIN_CACHE +#ifdef CONFIG_BFIN_ICACHE #define L1_CODE_LENGTH (0x14000 - 0x4000) #else #define L1_CODE_LENGTH 0x14000 #endif -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /* Memory Map for ADSP-BF532 processors */ @@ -102,36 +102,36 @@ #define L1_DATA_A_START 0xFF804000 #define L1_DATA_B_START 0xFF904000 -#ifdef CONFIG_BLKFIN_CACHE +#ifdef CONFIG_BFIN_ICACHE #define L1_CODE_LENGTH (0xC000 - 0x4000) #else #define L1_CODE_LENGTH 0xC000 #endif -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE -#ifdef CONFIG_BLKFIN_DCACHE_BANKA +#ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) #define L1_DATA_B_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (32*1024) -#define BLKFIN_DSUPBANKS 2 +#define BFIN_DCACHESIZE (32*1024) +#define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 #define L1_DATA_B_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 -#endif /*CONFIG_BLKFIN_DCACHE*/ +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 +#endif /*CONFIG_BFIN_DCACHE*/ #endif /* Memory Map for ADSP-BF531 processors */ @@ -144,16 +144,16 @@ #define L1_DATA_B_LENGTH 0x0000 -#ifdef CONFIG_BLKFIN_DCACHE +#ifdef CONFIG_BFIN_DCACHE #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x4000 - 0x4000) -#define BLKFIN_DCACHESIZE (16*1024) -#define BLKFIN_DSUPBANKS 1 +#define BFIN_DCACHESIZE (16*1024) +#define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x4000 -#define BLKFIN_DCACHESIZE (0*1024) -#define BLKFIN_DSUPBANKS 0 +#define BFIN_DCACHESIZE (0*1024) +#define BFIN_DSUPBANKS 0 #endif #endif |