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authorKe Wei <kewei@marvell.com>2008-05-23 12:23:22 +0400
committerLennert Buytenhek <buytenh@marvell.com>2008-06-23 00:45:01 +0400
commit1219715de70956557b9dedf3ee021a73d4f4ec52 (patch)
tree8d778c742bb7e5a0f087e8f8f88a210da6f0125a /include/asm-arm/arch-orion5x
parentab6d15d50637fc25ee941710b23fed09ceb28db3 (diff)
downloadlinux-1219715de70956557b9dedf3ee021a73d4f4ec52.tar.xz
[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define
Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'include/asm-arm/arch-orion5x')
-rw-r--r--include/asm-arm/arch-orion5x/orion5x.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 20f7b406a798..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -154,6 +154,7 @@
#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
+#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)