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| author | Carlo Caione <carlo@caione.org> | 2017-09-17 19:45:23 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-10-29 18:30:17 +0300 |
| commit | 4692142a3dc82d60f9f290f98a6e1f8f627ba90a (patch) | |
| tree | d98b4823f43890c18b37b4bd43e69ab243b5dcac /fs/dcache.c | |
| parent | 4a5a27116b447d00d0a0d3f554ea37ffe387657f (diff) | |
| download | linux-4692142a3dc82d60f9f290f98a6e1f8f627ba90a.tar.xz | |
ARM: dts: meson8b: add support for booting the secondary CPU cores
Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
cores
- a range in the SRAM specifically reserved for booting secondary CPU
cores
- the "enable-method" which activates booting the secondary CPU cores
This adds all required nodes and properties to boot the secondary CPU
cores.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'fs/dcache.c')
0 files changed, 0 insertions, 0 deletions