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authorPaul Burton <paul.burton@imgtec.com>2017-08-16 00:25:15 +0300
committerBjorn Helgaas <bhelgaas@google.com>2017-08-16 19:44:37 +0300
commitb8550f11bd40b7b6fd4622be4fd0f5aa958faee2 (patch)
tree286b8c63811df2acc8938e4599adeb2f3da6f2b9 /fs/ceph
parent5c125683fc18fa60cb26d18b26d8d622b90c7f3e (diff)
downloadlinux-b8550f11bd40b7b6fd4622be4fd0f5aa958faee2.tar.xz
PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3
The devicetree binding documentation for the Xilinx NWL PCIe root port bridge shows an example which uses an interrupt-map property to map PCI INTx interrupts to hardware IRQ numbers 1-4. The driver creates an IRQ domain with size 4, which therefore covers the hwirq range 0-3. This means that if we attempt to make use of the INTD interrupt then we're likely to hit a WARN() in irq_domain_associate() because INTD, or hwirw=4, is outside of the range covered by the IRQ domain. irq_domain_associate() will then return -EINVAL and we'll be unable to make use of INTD. Fix this by making use of the pci_irqd_intx_xlate() helper function to translate the 1-4 range used in the DT to a 0-3 range used within the driver, and stop adding 1 to decoded hwirq numbers. Whilst cleaning up INTx handling we make use of the new PCI_NUM_INTX macro & drop the custom INTX definitions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
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