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authorAriel Elior <ariele@broadcom.com>2012-01-26 10:01:45 +0400
committerDavid S. Miller <davem@davemloft.net>2012-01-26 22:39:51 +0400
commit8d7b02783bc2b05974f6e47c2be8157f3a9cd89e (patch)
tree09df8af0cc714abb5e3e8df907e1b2eec1ecf84c /drivers
parentd6cb17d5f8015717f6963d24d52b06292a4cb40a (diff)
downloadlinux-8d7b02783bc2b05974f6e47c2be8157f3a9cd89e.tar.xz
bnx2x: Support Queue Per Cos in 5771xx devices
Enable the use of up to three hardware queues for transmission. The queues are always dequed round robin (i.e. strict priority, PFC and ETS are not supported). This does allow the allocation of a seperate HW queue for low volume, high priority traffic which will be serviced more promptly. Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h7
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h4
2 files changed, 6 insertions, 5 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index bf27c54ff2e0..0dd22bb44f0d 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -984,10 +984,11 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
/* Function parameters */
start_params->mf_mode = bp->mf_mode;
start_params->sd_vlan_tag = bp->mf_ov;
- if (CHIP_IS_E1x(bp))
- start_params->network_cos_mode = OVERRIDE_COS;
- else
+
+ if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
start_params->network_cos_mode = STATIC_COS;
+ else /* CHIP_IS_E1X */
+ start_params->network_cos_mode = FW_WRR;
return bnx2x_func_state_change(bp, &func_params);
}
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
index 66da39f0c84a..f33bc5722e58 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
@@ -803,10 +803,10 @@ enum bnx2x_q_type {
};
#define BNX2X_PRIMARY_CID_INDEX 0
-#define BNX2X_MULTI_TX_COS_E1X 1
+#define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */
#define BNX2X_MULTI_TX_COS_E2_E3A0 2
#define BNX2X_MULTI_TX_COS_E3B0 3
-#define BNX2X_MULTI_TX_COS BNX2X_MULTI_TX_COS_E3B0
+#define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
struct bnx2x_queue_init_params {