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authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>2012-06-18 17:32:40 +0400
committerJohn W. Linville <linville@tuxdriver.com>2012-06-20 23:14:54 +0400
commit4ff6a9d200c66f192da61822c36ad14424e218d6 (patch)
treeb2ce62b7bc20aa2bedcea0581456c3090b786130 /drivers
parent0967d862315366e2ef2401301ff2b1756928b4c1 (diff)
downloadlinux-4ff6a9d200c66f192da61822c36ad14424e218d6.tar.xz
ath9k_hw: fix LNA control on WLAN sleep
When WLAN enter full sleep mode, WLAN HW should send out a LNA_TAKE message for BT to take control of the shared LNA. Otherwise BT traffic is completely stopped whenever the wlan interface is moved full sleep mode. Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
index 867238f9d139..61558375bfbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
@@ -1015,9 +1015,14 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
return;
if (mci->is_2g) {
- ar9003_mci_send_2g5g_status(ah, true);
+ if (!force) {
+ ar9003_mci_send_2g5g_status(ah, true);
- REG_SET_BIT(ah, AR_MCI_TX_CTRL,
+ ar9003_mci_send_lna_transfer(ah, true);
+ udelay(5);
+ }
+
+ REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
@@ -1025,6 +1030,11 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
ar9003_mci_osla_setup(ah, true);
} else {
+ if (!force) {
+ ar9003_mci_send_lna_take(ah, true);
+ udelay(5);
+ }
+
REG_SET_BIT(ah, AR_MCI_TX_CTRL,
AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
@@ -1251,6 +1261,9 @@ void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
ath_dbg(common, MCI, "Give LNA and SPDT control to BT\n");
+ ar9003_mci_send_lna_take(ah, true);
+ udelay(50);
+
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
mci->is_2g = false;
mci->update_2g5g = true;