summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
authorMikael Pettersson <mikpe@it.uu.se>2006-12-01 12:55:58 +0300
committerJeff Garzik <jeff@garzik.org>2006-12-03 16:05:14 +0300
commit599b7202c5bf2c7345ea34007379ba241c94a491 (patch)
treeccadf142dd726377376ecaf1df9ecf355b1237e3 /drivers
parent800b399669ad495ad4361d134df87401ae36f44f (diff)
downloadlinux-599b7202c5bf2c7345ea34007379ba241c94a491.tar.xz
[PATCH] sata_promise: PHYMODE4 fixup
This patch adds code to fix up the PHYMODE4 "align timing" register value on second-generation Promise SATA chips. Failure to correct this value on non-x86 machines makes drive detection prone to failure due to timeouts. (I've observed about 50% detection failure rates on SPARC64.) The HW boots with a bad value in this register, but on x86 machines the Promise BIOS corrects it to the value recommended by the manual, so most people have been unaffected by this issue. After developing the patch I checked Promise's SATAII driver, and discovered that it also corrects PHYMODE4 just like this patch does. This patch depends on the sata_promise SATAII updates patch I sent recently. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/sata_promise.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index 8daf5d67dfe2..a2778cf016bc 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -280,6 +280,7 @@ static struct pci_driver pdc_ata_pci_driver = {
static int pdc_port_start(struct ata_port *ap)
{
struct device *dev = ap->host->dev;
+ struct pdc_host_priv *hp = ap->host->private_data;
struct pdc_port_priv *pp;
int rc;
@@ -301,6 +302,16 @@ static int pdc_port_start(struct ata_port *ap)
ap->private_data = pp;
+ /* fix up PHYMODE4 align timing */
+ if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
+ void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
+ unsigned int tmp;
+
+ tmp = readl(mmio + 0x014);
+ tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
+ writel(tmp, mmio + 0x014);
+ }
+
return 0;
err_out_kfree: