diff options
| author | Wenpeng Liang <liangwenpeng@huawei.com> | 2021-06-16 13:01:25 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-06-16 22:34:07 +0300 |
| commit | 33ab463220e59a74e803e4fc1c589c28b241b0ab (patch) | |
| tree | 9d90e5c4ee7df983f8ef3602ddfcc4971d6b4474 /drivers | |
| parent | 450bf1f0c60e818d3da927f8a2d272559ef1915b (diff) | |
| download | linux-33ab463220e59a74e803e4fc1c589c28b241b0ab.tar.xz | |
net: phy: remove unnecessary line continuation
Avoid unnecessary line continuations, and put '|' at the end of line.
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/dp83640.c | 4 | ||||
| -rw-r--r-- | drivers/net/phy/et1011c.c | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index 10769bfb1298..705c16675b80 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -170,9 +170,9 @@ static ushort gpio_tab[GPIO_TABLE_SIZE] = { module_param(chosen_phy, int, 0444); module_param_array(gpio_tab, ushort, NULL, 0444); -MODULE_PARM_DESC(chosen_phy, \ +MODULE_PARM_DESC(chosen_phy, "The address of the PHY to use for the ancillary clock features"); -MODULE_PARM_DESC(gpio_tab, \ +MODULE_PARM_DESC(gpio_tab, "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c index 07bb484ba402..be1b71d7cab7 100644 --- a/drivers/net/phy/et1011c.c +++ b/drivers/net/phy/et1011c.c @@ -73,10 +73,10 @@ static int et1011c_read_status(struct phy_device *phydev) ET1011C_GIGABIT_SPEED) { val = phy_read(phydev, ET1011C_CONFIG_REG); val &= ~ET1011C_TX_FIFO_MASK; - phy_write(phydev, ET1011C_CONFIG_REG, val\ - | ET1011C_GMII_INTERFACE\ - | ET1011C_SYS_CLK_EN\ - | ET1011C_TX_FIFO_DEPTH_16); + phy_write(phydev, ET1011C_CONFIG_REG, val | + ET1011C_GMII_INTERFACE | + ET1011C_SYS_CLK_EN | + ET1011C_TX_FIFO_DEPTH_16); } } |