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| author | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 04:42:53 +0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-09 04:42:53 +0400 |
| commit | 83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7 (patch) | |
| tree | bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce /drivers | |
| parent | 9308add6ea4fedeba37b0d7c4630a542bd34f214 (diff) | |
| download | linux-83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7.tar.xz | |
dmaengine, async_tx: support alignment checks
Some engines have transfer size and address alignment restrictions. Add
a per-operation alignment property to struct dma_device that the async
routines and dmatest can use to check alignment capabilities.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/dma/dmatest.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 58e49e41c7a3..a3722a7384b5 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -288,6 +288,7 @@ static int dmatest_func(void *data) dma_addr_t dma_dsts[dst_cnt]; struct completion cmp; unsigned long tmo = msecs_to_jiffies(3000); + u8 align = 0; total_tests++; @@ -295,6 +296,18 @@ static int dmatest_func(void *data) src_off = dmatest_random() % (test_buf_size - len + 1); dst_off = dmatest_random() % (test_buf_size - len + 1); + /* honor alignment restrictions */ + if (thread->type == DMA_MEMCPY) + align = dev->copy_align; + else if (thread->type == DMA_XOR) + align = dev->xor_align; + else if (thread->type == DMA_PQ) + align = dev->pq_align; + + len = (len >> align) << align; + src_off = (src_off >> align) << align; + dst_off = (dst_off >> align) << align; + dmatest_init_srcs(thread->srcs, src_off, len); dmatest_init_dsts(thread->dsts, dst_off, len); @@ -311,6 +324,7 @@ static int dmatest_func(void *data) DMA_BIDIRECTIONAL); } + if (thread->type == DMA_MEMCPY) tx = dev->device_prep_dma_memcpy(chan, dma_dsts[0] + dst_off, |