diff options
| author | Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com> | 2008-02-09 01:52:41 +0300 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2008-02-14 14:11:01 +0300 |
| commit | a0620156b05f2e1b77801e8bca724d0ed650974d (patch) | |
| tree | 8f3412a71e3ba001f65091fdfe55f7861f690bfe /drivers | |
| parent | a7faa8dc95ef90593d605d36409ef9100bdd11f8 (diff) | |
| download | linux-a0620156b05f2e1b77801e8bca724d0ed650974d.tar.xz | |
[POWERPC] PS3: Fix reading pm interval in logical performance monitor
ps3_read_pm (pm_interval) should return an actual HW register value
because the pm_interval register is a counter register.
This removes the shadow pm_interval register.
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ps3/ps3-lpm.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/ps3/ps3-lpm.c b/drivers/ps3/ps3-lpm.c index 8a0b16bad8e9..6c9592ce4996 100644 --- a/drivers/ps3/ps3-lpm.c +++ b/drivers/ps3/ps3-lpm.c @@ -76,7 +76,6 @@ * * @pm_control: Shadow of the processor's pm_control register. * @pm_start_stop: Shadow of the processor's pm_start_stop register. - * @pm_interval: Shadow of the processor's pm_interval register. * @group_control: Shadow of the processor's group_control register. * @debug_bus_control: Shadow of the processor's debug_bus_control register. * @@ -91,7 +90,6 @@ struct ps3_lpm_shadow_regs { u64 pm_control; u64 pm_start_stop; - u64 pm_interval; u64 group_control; u64 debug_bus_control; }; @@ -408,7 +406,14 @@ u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg) case pm_start_stop: return lpm_priv->shadow.pm_start_stop; case pm_interval: - return lpm_priv->shadow.pm_interval; + result = lv1_set_lpm_interval(lpm_priv->lpm_id, 0, 0, &val); + if (result) { + val = 0; + dev_dbg(sbd_core(), "%s:%u: lv1 set_inteval failed: " + "reg %u, %s\n", __func__, __LINE__, reg, + ps3_result(result)); + } + return (u32)val; case group_control: return lpm_priv->shadow.group_control; case debug_bus_control: @@ -475,10 +480,8 @@ void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) lpm_priv->shadow.pm_control = val; break; case pm_interval: - if (val != lpm_priv->shadow.pm_interval) - result = lv1_set_lpm_interval(lpm_priv->lpm_id, val, - PS3_WRITE_PM_MASK, &dummy); - lpm_priv->shadow.pm_interval = val; + result = lv1_set_lpm_interval(lpm_priv->lpm_id, val, + PS3_WRITE_PM_MASK, &dummy); break; case pm_start_stop: if (val != lpm_priv->shadow.pm_start_stop) @@ -1140,7 +1143,6 @@ int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache, lpm_priv->shadow.pm_control = PS3_LPM_SHADOW_REG_INIT; lpm_priv->shadow.pm_start_stop = PS3_LPM_SHADOW_REG_INIT; - lpm_priv->shadow.pm_interval = PS3_LPM_SHADOW_REG_INIT; lpm_priv->shadow.group_control = PS3_LPM_SHADOW_REG_INIT; lpm_priv->shadow.debug_bus_control = PS3_LPM_SHADOW_REG_INIT; |