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authorTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-11-16 11:55:44 +0300
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-11-17 16:56:50 +0300
commit801388cb168da9a63f0b4e839a7927d4c0e2b5cb (patch)
tree50112e832b9164dea4f7968c6a65821356783c38 /drivers
parent6315b5d33a8ff6e0bf3d083524ffaa4e33d5981b (diff)
downloadlinux-801388cb168da9a63f0b4e839a7927d4c0e2b5cb.tar.xz
drm/i915: Fix for_each_pipe argument in vlv_display_power_well_init
Macro takes dev_priv and not dev. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 379755d61109..356c662ad453 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1066,7 +1066,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
*
* CHV DPLL B/C have some issues if VGA mode is enabled.
*/
- for_each_pipe(&dev_priv->drm, pipe) {
+ for_each_pipe(dev_priv, pipe) {
u32 val = I915_READ(DPLL(pipe));
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;