diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2011-04-25 16:42:45 +0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-04-26 11:07:01 +0400 |
| commit | 0aebff4871d26410ae485b521870bb0ffe1736f0 (patch) | |
| tree | 48b869f07b111561307a26199bcec47b473c548d /drivers | |
| parent | bf734843120b905bacc3d24c88d7455ae70bf6e1 (diff) | |
| download | linux-0aebff4871d26410ae485b521870bb0ffe1736f0.tar.xz | |
tg3: Fix int generation hw bug for 5719 / 5720
On the 5719 and 5720, there is a bug where the hardware will
misinterpret a status tag update and leave interrupts permanently
disabled. This patch enables a hardware fix that works around the
issue.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tg3.c | 3 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 693f36e94dab..a72d0314ca78 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -8198,6 +8198,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; + if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && + GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) + val |= DMA_RWCTRL_TAGGED_STAT_WA; tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index eaa76694efb5..6f37d2a23544 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -188,6 +188,7 @@ #define METAL_REV_B2 0x02 #define TG3PCI_DMA_RW_CTRL 0x0000006c #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 +#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 |