diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2010-10-08 03:44:50 +0400 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2010-10-08 04:08:32 +0400 |
| commit | 5fc6d897fde352bad5db5767e7260741a8cdd9e9 (patch) | |
| tree | cb918dd33b8288aadead08b04b9f308f9d8bcbd1 /drivers | |
| parent | 400fb7f6a0cfe13025cb0296fdb4737da7025a8a (diff) | |
| download | linux-5fc6d897fde352bad5db5767e7260741a8cdd9e9.tar.xz | |
async_tx: make async_tx channel switching opt-in
The majority of drivers in drivers/dma/ will never establish cross
channel operation chains and do not need the extra overhead in struct
dma_async_tx_descriptor. Make channel switching opt-in by default.
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Ira Snyder <iws@ovro.caltech.edu>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/dma/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/dma/dmaengine.c | 4 |
2 files changed, 7 insertions, 4 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index ab28f6093414..79d1542f31c0 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -46,7 +46,7 @@ config INTEL_MID_DMAC If unsure, say N. -config ASYNC_TX_DISABLE_CHANNEL_SWITCH +config ASYNC_TX_ENABLE_CHANNEL_SWITCH bool config AMBA_PL08X @@ -62,7 +62,6 @@ config INTEL_IOATDMA depends on PCI && X86 select DMA_ENGINE select DCA - select ASYNC_TX_DISABLE_CHANNEL_SWITCH select ASYNC_TX_DISABLE_PQ_VAL_DMA select ASYNC_TX_DISABLE_XOR_VAL_DMA help @@ -77,6 +76,7 @@ config INTEL_IOP_ADMA tristate "Intel IOP ADMA support" depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH help Enable support for the Intel(R) IOP Series RAID engines. @@ -101,6 +101,7 @@ config FSL_DMA tristate "Freescale Elo and Elo Plus DMA support" depends on FSL_SOC select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH ---help--- Enable support for the Freescale Elo and Elo Plus DMA controllers. The Elo is the DMA controller on some 82xx and 83xx parts, and the @@ -117,6 +118,7 @@ config MV_XOR bool "Marvell XOR engine support" depends on PLAT_ORION select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH ---help--- Enable support for the Marvell XOR engine. @@ -174,6 +176,7 @@ config AMCC_PPC440SPE_ADMA depends on 440SPe || 440SP select DMA_ENGINE select ARCH_HAS_ASYNC_TX_FIND_CHANNEL + select ASYNC_TX_ENABLE_CHANNEL_SWITCH help Enable support for the AMCC PPC440SPe RAID engines. diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 235153cd7ac5..8bcb15fb959d 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -706,7 +706,7 @@ int dma_async_device_register(struct dma_device *device) BUG_ON(!device->dev); /* note: this only matters in the - * CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH=y case + * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case */ if (device_has_all_tx_types(device)) dma_cap_set(DMA_ASYNC_TX, device->cap_mask); @@ -980,7 +980,7 @@ void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, struct dma_chan *chan) { tx->chan = chan; - #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH + #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH spin_lock_init(&tx->lock); #endif } |