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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-07-31 09:21:07 +0300
committerLinus Walleij <linus.walleij@linaro.org>2017-08-14 16:01:00 +0300
commite3829d15460feb884805012c72ec4a17402822eb (patch)
treed5d178991f09be26699a4f5bdb875b8444f90837 /drivers/vlynq
parent9fc939c68325752580ffcf966e9da49a7ab94a90 (diff)
downloadlinux-e3829d15460feb884805012c72ec4a17402822eb.tar.xz
pinctrl: uniphier: fix pin_config_get() for input-enable
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are located across multiple registers. So, the register offset must be taken into account. Otherwise, wrong input-enable status is displayed. While we here, rename the macro because it is a base address. Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/vlynq')
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