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authorIan Abbott <abbotti@mev.co.uk>2014-07-03 17:46:39 +0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2014-08-26 16:36:51 +0400
commit4d4e2c003bd6c6bdd85080bd096d54d5d251defa (patch)
tree203fe72f2f30bc3524f5dc3ca64724e8b175d780 /drivers/video
parent62795a0d81970bfdd5866ffd87160c670a6b344c (diff)
downloadlinux-4d4e2c003bd6c6bdd85080bd096d54d5d251defa.tar.xz
video: da8xx-fb: preserve display width when changing HSYNC
When looking at this driver for a client, I noticed the code that configures the HSYNC pulse clobbers the display width in the same register. It only preserves the MS part of the width in bit 3 and zeros the LS part of the width in bits 9 to 4. This doesn't matter during initialization as the width is configured afterwards, but subsequent use of the FBIPUT_HSYNC ioctl would clobber the width. Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the horizontal sync. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/fbdev/da8xx-fb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/fbdev/da8xx-fb.c b/drivers/video/fbdev/da8xx-fb.c
index 788f6b37fce7..10c876c95772 100644
--- a/drivers/video/fbdev/da8xx-fb.c
+++ b/drivers/video/fbdev/da8xx-fb.c
@@ -419,7 +419,7 @@ static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
{
u32 reg;
- reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
+ reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
reg |= (((back_porch-1) & 0xff) << 24)
| (((front_porch-1) & 0xff) << 16)
| (((pulse_width-1) & 0x3f) << 10);